Lines Matching +full:24 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk-provider.h>
26 #include "ccu-sun4i-a10.h"
29 .enable = BIT(31),
36 .hw.init = CLK_HW_INIT("pll-core",
48 * With sigma-delta modulation for fractional-N on the audio PLL,
63 .enable = BIT(31),
67 0x00c, BIT(31)),
71 .hw.init = CLK_HW_INIT("pll-audio-base",
80 .enable = BIT(31),
82 .frac = _SUNXI_CCU_FRAC(BIT(15), BIT(14),
89 .hw.init = CLK_HW_INIT("pll-video0",
97 .enable = BIT(31),
104 .hw.init = CLK_HW_INIT("pll-ve",
112 .enable = BIT(31),
117 .hw.init = CLK_HW_INIT("pll-ve",
125 .enable = BIT(31),
130 .hw.init = CLK_HW_INIT("pll-ddr-base",
137 static SUNXI_CCU_M(pll_ddr_clk, "pll-ddr", "pll-ddr-base", 0x020, 0, 2,
144 .hw.init = CLK_HW_INIT("pll-ddr-other", "pll-ddr-base",
151 .enable = BIT(31),
156 .hw.init = CLK_HW_INIT("pll-periph-base",
163 static CLK_FIXED_FACTOR_HW(pll_periph_clk, "pll-periph",
169 .enable = BIT(14),
175 .hw.init = CLK_HW_INIT("pll-periph-sata",
176 "pll-periph-base",
182 .enable = BIT(31),
184 .frac = _SUNXI_CCU_FRAC(BIT(15), BIT(14),
191 .hw.init = CLK_HW_INIT("pll-video1",
200 .enable = BIT(31),
205 .hw.init = CLK_HW_INIT("pll-gpu",
212 static SUNXI_CCU_GATE(hosc_clk, "hosc", "osc24M", 0x050, BIT(0), 0);
215 "pll-core", "pll-periph" };
248 static const char *const ahb_sun7i_parents[] = { "axi", "pll-periph",
249 "pll-periph" };
282 static const char *const apb1_parents[] = { "hosc", "pll-periph", "osc32k" };
286 24, 2, /* mux */
290 static SUNXI_CCU_GATE(axi_dram_clk, "axi-dram", "ahb",
291 0x05c, BIT(31), 0);
293 static SUNXI_CCU_GATE(ahb_otg_clk, "ahb-otg", "ahb",
294 0x060, BIT(0), 0);
295 static SUNXI_CCU_GATE(ahb_ehci0_clk, "ahb-ehci0", "ahb",
296 0x060, BIT(1), 0);
297 static SUNXI_CCU_GATE(ahb_ohci0_clk, "ahb-ohci0", "ahb",
298 0x060, BIT(2), 0);
299 static SUNXI_CCU_GATE(ahb_ehci1_clk, "ahb-ehci1", "ahb",
300 0x060, BIT(3), 0);
301 static SUNXI_CCU_GATE(ahb_ohci1_clk, "ahb-ohci1", "ahb",
302 0x060, BIT(4), 0);
303 static SUNXI_CCU_GATE(ahb_ss_clk, "ahb-ss", "ahb",
304 0x060, BIT(5), 0);
305 static SUNXI_CCU_GATE(ahb_dma_clk, "ahb-dma", "ahb",
306 0x060, BIT(6), 0);
307 static SUNXI_CCU_GATE(ahb_bist_clk, "ahb-bist", "ahb",
308 0x060, BIT(7), 0);
309 static SUNXI_CCU_GATE(ahb_mmc0_clk, "ahb-mmc0", "ahb",
310 0x060, BIT(8), 0);
311 static SUNXI_CCU_GATE(ahb_mmc1_clk, "ahb-mmc1", "ahb",
312 0x060, BIT(9), 0);
313 static SUNXI_CCU_GATE(ahb_mmc2_clk, "ahb-mmc2", "ahb",
314 0x060, BIT(10), 0);
315 static SUNXI_CCU_GATE(ahb_mmc3_clk, "ahb-mmc3", "ahb",
316 0x060, BIT(11), 0);
317 static SUNXI_CCU_GATE(ahb_ms_clk, "ahb-ms", "ahb",
318 0x060, BIT(12), 0);
319 static SUNXI_CCU_GATE(ahb_nand_clk, "ahb-nand", "ahb",
320 0x060, BIT(13), 0);
321 static SUNXI_CCU_GATE(ahb_sdram_clk, "ahb-sdram", "ahb",
322 0x060, BIT(14), CLK_IS_CRITICAL);
324 static SUNXI_CCU_GATE(ahb_ace_clk, "ahb-ace", "ahb",
325 0x060, BIT(16), 0);
326 static SUNXI_CCU_GATE(ahb_emac_clk, "ahb-emac", "ahb",
327 0x060, BIT(17), 0);
328 static SUNXI_CCU_GATE(ahb_ts_clk, "ahb-ts", "ahb",
329 0x060, BIT(18), 0);
330 static SUNXI_CCU_GATE(ahb_spi0_clk, "ahb-spi0", "ahb",
331 0x060, BIT(20), 0);
332 static SUNXI_CCU_GATE(ahb_spi1_clk, "ahb-spi1", "ahb",
333 0x060, BIT(21), 0);
334 static SUNXI_CCU_GATE(ahb_spi2_clk, "ahb-spi2", "ahb",
335 0x060, BIT(22), 0);
336 static SUNXI_CCU_GATE(ahb_spi3_clk, "ahb-spi3", "ahb",
337 0x060, BIT(23), 0);
338 static SUNXI_CCU_GATE(ahb_pata_clk, "ahb-pata", "ahb",
339 0x060, BIT(24), 0);
341 static SUNXI_CCU_GATE(ahb_sata_clk, "ahb-sata", "ahb",
342 0x060, BIT(25), 0);
344 static SUNXI_CCU_GATE(ahb_gps_clk, "ahb-gps", "ahb",
345 0x060, BIT(26), 0);
347 static SUNXI_CCU_GATE(ahb_hstimer_clk, "ahb-hstimer", "ahb",
348 0x060, BIT(28), 0);
350 static SUNXI_CCU_GATE(ahb_ve_clk, "ahb-ve", "ahb",
351 0x064, BIT(0), 0);
352 static SUNXI_CCU_GATE(ahb_tvd_clk, "ahb-tvd", "ahb",
353 0x064, BIT(1), 0);
354 static SUNXI_CCU_GATE(ahb_tve0_clk, "ahb-tve0", "ahb",
355 0x064, BIT(2), 0);
356 static SUNXI_CCU_GATE(ahb_tve1_clk, "ahb-tve1", "ahb",
357 0x064, BIT(3), 0);
358 static SUNXI_CCU_GATE(ahb_lcd0_clk, "ahb-lcd0", "ahb",
359 0x064, BIT(4), 0);
360 static SUNXI_CCU_GATE(ahb_lcd1_clk, "ahb-lcd1", "ahb",
361 0x064, BIT(5), 0);
362 static SUNXI_CCU_GATE(ahb_csi0_clk, "ahb-csi0", "ahb",
363 0x064, BIT(8), 0);
364 static SUNXI_CCU_GATE(ahb_csi1_clk, "ahb-csi1", "ahb",
365 0x064, BIT(9), 0);
367 static SUNXI_CCU_GATE(ahb_hdmi1_clk, "ahb-hdmi1", "ahb",
368 0x064, BIT(10), 0);
369 static SUNXI_CCU_GATE(ahb_hdmi0_clk, "ahb-hdmi0", "ahb",
370 0x064, BIT(11), 0);
371 static SUNXI_CCU_GATE(ahb_de_be0_clk, "ahb-de-be0", "ahb",
372 0x064, BIT(12), 0);
373 static SUNXI_CCU_GATE(ahb_de_be1_clk, "ahb-de-be1", "ahb",
374 0x064, BIT(13), 0);
375 static SUNXI_CCU_GATE(ahb_de_fe0_clk, "ahb-de-fe0", "ahb",
376 0x064, BIT(14), 0);
377 static SUNXI_CCU_GATE(ahb_de_fe1_clk, "ahb-de-fe1", "ahb",
378 0x064, BIT(15), 0);
380 static SUNXI_CCU_GATE(ahb_gmac_clk, "ahb-gmac", "ahb",
381 0x064, BIT(17), 0);
382 static SUNXI_CCU_GATE(ahb_mp_clk, "ahb-mp", "ahb",
383 0x064, BIT(18), 0);
384 static SUNXI_CCU_GATE(ahb_gpu_clk, "ahb-gpu", "ahb",
385 0x064, BIT(20), 0);
387 static SUNXI_CCU_GATE(apb0_codec_clk, "apb0-codec", "apb0",
388 0x068, BIT(0), 0);
389 static SUNXI_CCU_GATE(apb0_spdif_clk, "apb0-spdif", "apb0",
390 0x068, BIT(1), 0);
391 static SUNXI_CCU_GATE(apb0_ac97_clk, "apb0-ac97", "apb0",
392 0x068, BIT(2), 0);
393 static SUNXI_CCU_GATE(apb0_i2s0_clk, "apb0-i2s0", "apb0",
394 0x068, BIT(3), 0);
396 static SUNXI_CCU_GATE(apb0_i2s1_clk, "apb0-i2s1", "apb0",
397 0x068, BIT(4), 0);
398 static SUNXI_CCU_GATE(apb0_pio_clk, "apb0-pio", "apb0",
399 0x068, BIT(5), 0);
400 static SUNXI_CCU_GATE(apb0_ir0_clk, "apb0-ir0", "apb0",
401 0x068, BIT(6), 0);
402 static SUNXI_CCU_GATE(apb0_ir1_clk, "apb0-ir1", "apb0",
403 0x068, BIT(7), 0);
405 static SUNXI_CCU_GATE(apb0_i2s2_clk, "apb0-i2s2", "apb0",
406 0x068, BIT(8), 0);
407 static SUNXI_CCU_GATE(apb0_keypad_clk, "apb0-keypad", "apb0",
408 0x068, BIT(10), 0);
410 static SUNXI_CCU_GATE(apb1_i2c0_clk, "apb1-i2c0", "apb1",
411 0x06c, BIT(0), 0);
412 static SUNXI_CCU_GATE(apb1_i2c1_clk, "apb1-i2c1", "apb1",
413 0x06c, BIT(1), 0);
414 static SUNXI_CCU_GATE(apb1_i2c2_clk, "apb1-i2c2", "apb1",
415 0x06c, BIT(2), 0);
417 static SUNXI_CCU_GATE(apb1_i2c3_clk, "apb1-i2c3", "apb1",
418 0x06c, BIT(3), 0);
419 static SUNXI_CCU_GATE(apb1_can_clk, "apb1-can", "apb1",
420 0x06c, BIT(4), 0);
421 static SUNXI_CCU_GATE(apb1_scr_clk, "apb1-scr", "apb1",
422 0x06c, BIT(5), 0);
423 static SUNXI_CCU_GATE(apb1_ps20_clk, "apb1-ps20", "apb1",
424 0x06c, BIT(6), 0);
425 static SUNXI_CCU_GATE(apb1_ps21_clk, "apb1-ps21", "apb1",
426 0x06c, BIT(7), 0);
428 static SUNXI_CCU_GATE(apb1_i2c4_clk, "apb1-i2c4", "apb1",
429 0x06c, BIT(15), 0);
430 static SUNXI_CCU_GATE(apb1_uart0_clk, "apb1-uart0", "apb1",
431 0x06c, BIT(16), 0);
432 static SUNXI_CCU_GATE(apb1_uart1_clk, "apb1-uart1", "apb1",
433 0x06c, BIT(17), 0);
434 static SUNXI_CCU_GATE(apb1_uart2_clk, "apb1-uart2", "apb1",
435 0x06c, BIT(18), 0);
436 static SUNXI_CCU_GATE(apb1_uart3_clk, "apb1-uart3", "apb1",
437 0x06c, BIT(19), 0);
438 static SUNXI_CCU_GATE(apb1_uart4_clk, "apb1-uart4", "apb1",
439 0x06c, BIT(20), 0);
440 static SUNXI_CCU_GATE(apb1_uart5_clk, "apb1-uart5", "apb1",
441 0x06c, BIT(21), 0);
442 static SUNXI_CCU_GATE(apb1_uart6_clk, "apb1-uart6", "apb1",
443 0x06c, BIT(22), 0);
444 static SUNXI_CCU_GATE(apb1_uart7_clk, "apb1-uart7", "apb1",
445 0x06c, BIT(23), 0);
447 static const char *const mod0_default_parents[] = { "hosc", "pll-periph",
448 "pll-ddr-other" };
452 24, 2, /* mux */
453 BIT(31), /* gate */
460 24, 2, /* mux */
461 BIT(31), /* gate */
467 24, 2, /* mux */
468 BIT(31), /* gate */
480 24, 2, /* mux */
481 BIT(31), /* gate */
493 24, 2, /* mux */
494 BIT(31), /* gate */
506 24, 2, /* mux */
507 BIT(31), /* gate */
519 24, 2, /* mux */
520 BIT(31), /* gate */
526 24, 2, /* mux */
527 BIT(31), /* gate */
533 24, 2, /* mux */
534 BIT(31), /* gate */
540 24, 2, /* mux */
541 BIT(31), /* gate */
547 24, 2, /* mux */
548 BIT(31), /* gate */
555 24, 2, /* mux */
556 BIT(31), /* gate */
560 static const char *const ir_parents_sun4i[] = { "hosc", "pll-periph",
561 "pll-ddr-other" };
565 24, 2, /* mux */
566 BIT(31), /* gate */
572 24, 2, /* mux */
573 BIT(31), /* gate */
575 static const char *const ir_parents_sun7i[] = { "hosc", "pll-periph",
576 "pll-ddr-other", "osc32k" };
580 24, 2, /* mux */
581 BIT(31), /* gate */
587 24, 2, /* mux */
588 BIT(31), /* gate */
591 static const char *const audio_parents[] = { "pll-audio-8x", "pll-audio-4x",
592 "pll-audio-2x", "pll-audio" };
594 0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
597 0x0bc, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
601 0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
606 .enable = BIT(31),
609 .mux = _SUNXI_CCU_MUX_TABLE(24, 2, keypad_table),
620 * SATA supports external clock as parent via BIT(24) and is probably an
622 * SATA-CLKM / SATA-CLKP pins.
624 static const char *const sata_parents[] = {"pll-periph-sata", "sata-ext"};
626 0x0c8, 24, 1, BIT(31), CLK_SET_RATE_PARENT);
629 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "pll-periph",
630 0x0cc, BIT(6), 0);
631 static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "pll-periph",
632 0x0cc, BIT(7), 0);
633 static SUNXI_CCU_GATE(usb_phy_clk, "usb-phy", "pll-periph",
634 0x0cc, BIT(8), 0);
641 24, 2, /* mux */
642 BIT(31), /* gate */
647 0x0d8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
651 0x0dc, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
653 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "pll-ddr",
654 0x100, BIT(0), 0);
655 static SUNXI_CCU_GATE(dram_csi0_clk, "dram-csi0", "pll-ddr",
656 0x100, BIT(1), 0);
657 static SUNXI_CCU_GATE(dram_csi1_clk, "dram-csi1", "pll-ddr",
658 0x100, BIT(2), 0);
659 static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "pll-ddr",
660 0x100, BIT(3), 0);
661 static SUNXI_CCU_GATE(dram_tvd_clk, "dram-tvd", "pll-ddr",
662 0x100, BIT(4), 0);
663 static SUNXI_CCU_GATE(dram_tve0_clk, "dram-tve0", "pll-ddr",
664 0x100, BIT(5), 0);
665 static SUNXI_CCU_GATE(dram_tve1_clk, "dram-tve1", "pll-ddr",
666 0x100, BIT(6), 0);
669 static SUNXI_CCU_GATE(dram_out_clk, "dram-out", "pll-ddr",
670 0x100, BIT(15), CLK_IS_CRITICAL);
671 static SUNXI_CCU_GATE(dram_de_fe1_clk, "dram-de-fe1", "pll-ddr",
672 0x100, BIT(24), 0);
673 static SUNXI_CCU_GATE(dram_de_fe0_clk, "dram-de-fe0", "pll-ddr",
674 0x100, BIT(25), 0);
675 static SUNXI_CCU_GATE(dram_de_be0_clk, "dram-de-be0", "pll-ddr",
676 0x100, BIT(26), 0);
677 static SUNXI_CCU_GATE(dram_de_be1_clk, "dram-de-be1", "pll-ddr",
678 0x100, BIT(27), 0);
679 static SUNXI_CCU_GATE(dram_mp_clk, "dram-mp", "pll-ddr",
680 0x100, BIT(28), 0);
681 static SUNXI_CCU_GATE(dram_ace_clk, "dram-ace", "pll-ddr",
682 0x100, BIT(29), 0);
684 static const char *const de_parents[] = { "pll-video0", "pll-video1",
685 "pll-ddr-other" };
686 static SUNXI_CCU_M_WITH_MUX_GATE(de_be0_clk, "de-be0", de_parents,
687 0x104, 0, 4, 24, 2, BIT(31), 0);
689 static SUNXI_CCU_M_WITH_MUX_GATE(de_be1_clk, "de-be1", de_parents,
690 0x108, 0, 4, 24, 2, BIT(31), 0);
692 static SUNXI_CCU_M_WITH_MUX_GATE(de_fe0_clk, "de-fe0", de_parents,
693 0x10c, 0, 4, 24, 2, BIT(31), 0);
695 static SUNXI_CCU_M_WITH_MUX_GATE(de_fe1_clk, "de-fe1", de_parents,
696 0x110, 0, 4, 24, 2, BIT(31), 0);
699 static SUNXI_CCU_M_WITH_MUX_GATE(de_mp_clk, "de-mp", de_parents,
700 0x114, 0, 4, 24, 2, BIT(31), 0);
702 static const char *const disp_parents[] = { "pll-video0", "pll-video1",
703 "pll-video0-2x", "pll-video1-2x" };
704 static SUNXI_CCU_MUX_WITH_GATE(tcon0_ch0_clk, "tcon0-ch0-sclk", disp_parents,
705 0x118, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
706 static SUNXI_CCU_MUX_WITH_GATE(tcon1_ch0_clk, "tcon1-ch0-sclk", disp_parents,
707 0x11c, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
709 static const char *const csi_sclk_parents[] = { "pll-video0", "pll-ve",
710 "pll-ddr-other", "pll-periph" };
712 static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk",
714 0x120, 0, 4, 24, 2, BIT(31), 0);
717 static const char *const tvd_parents[] = { "pll-video0", "pll-video1" };
719 0x128, 24, 1, BIT(31), 0);
723 "tvd-sclk2", tvd_parents,
728 BIT(15), /* gate */
731 static SUNXI_CCU_M_WITH_GATE(tvd_sclk1_sun7i_clk, "tvd-sclk1", "tvd-sclk2",
732 0x128, 0, 4, BIT(31), 0);
734 static SUNXI_CCU_M_WITH_MUX_GATE(tcon0_ch1_sclk2_clk, "tcon0-ch1-sclk2",
736 0x12c, 0, 4, 24, 2, BIT(31),
740 "tcon0-ch1-sclk1", "tcon0-ch1-sclk2",
741 0x12c, 11, 1, BIT(15),
744 static SUNXI_CCU_M_WITH_MUX_GATE(tcon1_ch1_sclk2_clk, "tcon1-ch1-sclk2",
746 0x130, 0, 4, 24, 2, BIT(31),
750 "tcon1-ch1-sclk1", "tcon1-ch1-sclk2",
751 0x130, 11, 1, BIT(15),
754 static const char *const csi_parents[] = { "hosc", "pll-video0", "pll-video1",
755 "pll-video0-2x", "pll-video1-2x"};
759 0x134, 0, 5, 24, 3, BIT(31), 0);
763 0x138, 0, 5, 24, 3, BIT(31), 0);
765 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", 0x13c, 16, 8, BIT(31), 0);
767 static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio",
768 0x140, BIT(31), CLK_SET_RATE_PARENT);
770 static SUNXI_CCU_GATE(avs_clk, "avs", "hosc", 0x144, BIT(31), 0);
772 static const char *const ace_parents[] = { "pll-ve", "pll-ddr-other" };
774 0x148, 0, 4, 24, 1, BIT(31), 0);
777 0x150, 0, 4, 24, 2, BIT(31),
780 static const char *const gpu_parents_sun4i[] = { "pll-video0", "pll-ve",
781 "pll-ddr-other",
782 "pll-video1" };
784 0x154, 0, 4, 24, 2, BIT(31),
787 static const char *const gpu_parents_sun7i[] = { "pll-video0", "pll-ve",
788 "pll-ddr-other", "pll-video1",
789 "pll-gpu" };
793 0x154, 0, 4, 24, 3, BIT(31),
796 static const char *const mbus_sun4i_parents[] = { "hosc", "pll-periph",
797 "pll-ddr-other" };
799 0x15c, 0, 4, 16, 2, 24, 2, BIT(31),
801 static const char *const mbus_sun7i_parents[] = { "hosc", "pll-periph-base",
802 "pll-ddr-other" };
804 0x15c, 0, 4, 16, 2, 24, 2, BIT(31),
807 static SUNXI_CCU_GATE(hdmi1_slow_clk, "hdmi1-slow", "hosc", 0x178, BIT(31), 0);
809 static const char *const hdmi1_parents[] = { "pll-video0", "pll-video1" };
813 0x17c, 0, 4, 24, 2, BIT(31),
822 .enable = BIT(31),
826 .shift = 24,
834 .hw.init = CLK_HW_INIT_PARENTS("out-a",
841 .enable = BIT(31),
845 .shift = 24,
853 .hw.init = CLK_HW_INIT_PARENTS("out-b",
1036 /* Post-divider for pll-audio is hardcoded to 1 */
1037 static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
1040 static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
1043 static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
1046 static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
1049 static CLK_FIXED_FACTOR_HW(pll_video0_2x_clk, "pll-video0-2x",
1052 static CLK_FIXED_FACTOR_HW(pll_video1_2x_clk, "pll-video1-2x",
1384 [RST_USB_PHY0] = { 0x0cc, BIT(0) },
1385 [RST_USB_PHY1] = { 0x0cc, BIT(1) },
1386 [RST_USB_PHY2] = { 0x0cc, BIT(2) },
1387 [RST_GPS] = { 0x0d0, BIT(0) },
1388 [RST_DE_BE0] = { 0x104, BIT(30) },
1389 [RST_DE_BE1] = { 0x108, BIT(30) },
1390 [RST_DE_FE0] = { 0x10c, BIT(30) },
1391 [RST_DE_FE1] = { 0x110, BIT(30) },
1392 [RST_DE_MP] = { 0x114, BIT(30) },
1393 [RST_TVE0] = { 0x118, BIT(29) },
1394 [RST_TCON0] = { 0x118, BIT(30) },
1395 [RST_TVE1] = { 0x11c, BIT(29) },
1396 [RST_TCON1] = { 0x11c, BIT(30) },
1397 [RST_CSI0] = { 0x134, BIT(30) },
1398 [RST_CSI1] = { 0x138, BIT(30) },
1399 [RST_VE] = { 0x13c, BIT(0) },
1400 [RST_ACE] = { 0x148, BIT(16) },
1401 [RST_LVDS] = { 0x14c, BIT(0) },
1402 [RST_GPU] = { 0x154, BIT(30) },
1403 [RST_HDMI_H] = { 0x170, BIT(0) },
1404 [RST_HDMI_SYS] = { 0x170, BIT(1) },
1405 [RST_HDMI_AUDIO_DMA] = { 0x170, BIT(2) },
1445 * settings interfere with sigma-delta modulation and result in sun4i_ccu_init()
1450 /* Force the PLL-Audio-1x divider to 1 */ in sun4i_ccu_init()
1474 CLK_OF_DECLARE(sun4i_a10_ccu, "allwinner,sun4i-a10-ccu",
1481 CLK_OF_DECLARE(sun7i_a20_ccu, "allwinner,sun7i-a20-ccu",