Lines Matching +full:24 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
23 #include "ccu-sun8i-a23-a33.h"
26 .enable = BIT(31),
27 .lock = BIT(28),
36 .hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
47 * With sigma-delta modulation for fractional-N on the audio PLL,
61 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
65 pll_audio_sdm_table, BIT(24),
66 0x284, BIT(31),
67 BIT(31), /* gate */
68 BIT(28), /* lock */
71 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
75 BIT(24), /* frac enable */
76 BIT(25), /* frac select */
79 BIT(31), /* gate */
80 BIT(28), /* lock */
83 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
87 BIT(24), /* frac enable */
88 BIT(25), /* frac select */
91 BIT(31), /* gate */
92 BIT(28), /* lock */
95 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
100 BIT(31), /* gate */
101 BIT(28), /* lock */
104 static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph_clk, "pll-periph",
108 BIT(31), /* gate */
109 BIT(28), /* lock */
110 2, /* post-div */
113 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
117 BIT(24), /* frac enable */
118 BIT(25), /* frac select */
121 BIT(31), /* gate */
122 BIT(28), /* lock */
128 * The MIPI mode is a standard NKM-style clock. The HDMI mode is an
133 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_mipi_clk, "pll-mipi",
134 "pll-video", 0x040,
138 BIT(31) | BIT(23) | BIT(22), /* gate */
139 BIT(28), /* lock */
142 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic",
146 BIT(24), /* frac enable */
147 BIT(25), /* frac select */
150 BIT(31), /* gate */
151 BIT(28), /* lock */
154 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
158 BIT(24), /* frac enable */
159 BIT(25), /* frac select */
162 BIT(31), /* gate */
163 BIT(28), /* lock */
167 .enable = BIT(31),
168 .lock = BIT(28),
172 .hw.init = CLK_HW_INIT("pll-ddr1", "osc24M",
179 "pll-cpux" , "pll-cpux" };
186 "axi" , "pll-periph" };
222 "pll-periph" , "pll-periph" };
226 24, 2, /* mux */
229 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
230 0x060, BIT(1), 0);
231 static SUNXI_CCU_GATE(bus_ss_clk, "bus-ss", "ahb1",
232 0x060, BIT(5), 0);
233 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
234 0x060, BIT(6), 0);
235 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
236 0x060, BIT(8), 0);
237 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
238 0x060, BIT(9), 0);
239 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
240 0x060, BIT(10), 0);
241 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
242 0x060, BIT(13), 0);
243 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
244 0x060, BIT(14), 0);
245 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
246 0x060, BIT(19), 0);
247 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
248 0x060, BIT(20), 0);
249 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1",
250 0x060, BIT(21), 0);
251 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
252 0x060, BIT(24), 0);
253 static SUNXI_CCU_GATE(bus_ehci_clk, "bus-ehci", "ahb1",
254 0x060, BIT(26), 0);
255 static SUNXI_CCU_GATE(bus_ohci_clk, "bus-ohci", "ahb1",
256 0x060, BIT(29), 0);
258 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1",
259 0x064, BIT(0), 0);
260 static SUNXI_CCU_GATE(bus_lcd_clk, "bus-lcd", "ahb1",
261 0x064, BIT(4), 0);
262 static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1",
263 0x064, BIT(8), 0);
264 static SUNXI_CCU_GATE(bus_de_be_clk, "bus-de-be", "ahb1",
265 0x064, BIT(12), 0);
266 static SUNXI_CCU_GATE(bus_de_fe_clk, "bus-de-fe", "ahb1",
267 0x064, BIT(14), 0);
268 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",
269 0x064, BIT(20), 0);
270 static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",
271 0x064, BIT(21), 0);
272 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
273 0x064, BIT(22), 0);
274 static SUNXI_CCU_GATE(bus_drc_clk, "bus-drc", "ahb1",
275 0x064, BIT(25), 0);
276 static SUNXI_CCU_GATE(bus_sat_clk, "bus-sat", "ahb1",
277 0x064, BIT(26), 0);
279 static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1",
280 0x068, BIT(0), 0);
281 static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",
282 0x068, BIT(5), 0);
283 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
284 0x068, BIT(12), 0);
285 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1",
286 0x068, BIT(13), 0);
288 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
289 0x06c, BIT(0), 0);
290 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
291 0x06c, BIT(1), 0);
292 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
293 0x06c, BIT(2), 0);
294 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
295 0x06c, BIT(16), 0);
296 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
297 0x06c, BIT(17), 0);
298 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
299 0x06c, BIT(18), 0);
300 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
301 0x06c, BIT(19), 0);
302 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2",
303 0x06c, BIT(20), 0);
305 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" };
309 24, 2, /* mux */
310 BIT(31), /* gate */
316 24, 2, /* mux */
317 BIT(31), /* gate */
328 24, 2, /* mux */
329 BIT(31), /* gate */
340 24, 2, /* mux */
341 BIT(31), /* gate */
352 24, 2, /* mux */
353 BIT(31), /* gate */
359 24, 2, /* mux */
360 BIT(31), /* gate */
366 24, 2, /* mux */
367 BIT(31), /* gate */
370 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
371 "pll-audio-2x", "pll-audio" };
373 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
376 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
379 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
380 0x0cc, BIT(8), 0);
381 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
382 0x0cc, BIT(9), 0);
383 static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic",
384 0x0cc, BIT(10), 0);
385 static SUNXI_CCU_GATE(usb_hsic_12M_clk, "usb-hsic-12M", "osc24M",
386 0x0cc, BIT(11), 0);
387 static SUNXI_CCU_GATE(usb_ohci_clk, "usb-ohci", "osc24M",
388 0x0cc, BIT(16), 0);
390 static SUNXI_CCU_M(dram_clk, "dram", "pll-ddr",
393 static const char * const pll_ddr_parents[] = { "pll-ddr0", "pll-ddr1" };
394 static SUNXI_CCU_MUX(pll_ddr_clk, "pll-ddr", pll_ddr_parents,
397 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram",
398 0x100, BIT(0), 0);
399 static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram",
400 0x100, BIT(1), 0);
401 static SUNXI_CCU_GATE(dram_drc_clk, "dram-drc", "dram",
402 0x100, BIT(16), 0);
403 static SUNXI_CCU_GATE(dram_de_fe_clk, "dram-de-fe", "dram",
404 0x100, BIT(24), 0);
405 static SUNXI_CCU_GATE(dram_de_be_clk, "dram-de-be", "dram",
406 0x100, BIT(26), 0);
408 static const char * const de_parents[] = { "pll-video", "pll-periph-2x",
409 "pll-gpu", "pll-de" };
411 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_be_clk, "de-be",
413 0x104, 0, 4, 24, 3, BIT(31), 0);
415 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_fe_clk, "de-fe",
417 0x10c, 0, 4, 24, 3, BIT(31), 0);
419 static const char * const lcd_ch0_parents[] = { "pll-video", "pll-video-2x",
420 "pll-mipi" };
422 static SUNXI_CCU_MUX_TABLE_WITH_GATE(lcd_ch0_clk, "lcd-ch0",
424 0x118, 24, 3, BIT(31),
427 static const char * const lcd_ch1_parents[] = { "pll-video", "pll-video-2x" };
429 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(lcd_ch1_clk, "lcd-ch1",
431 0x12c, 0, 4, 24, 2, BIT(31), 0);
433 static const char * const csi_sclk_parents[] = { "pll-video", "pll-de",
434 "pll-mipi", "pll-ve" };
436 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_sclk_clk, "csi-sclk",
438 0x134, 16, 4, 24, 3, BIT(31), 0);
440 static const char * const csi_mclk_parents[] = { "pll-video", "pll-de",
443 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_mclk_clk, "csi-mclk",
445 0x134, 0, 5, 8, 3, BIT(15), 0);
447 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
448 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
450 static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio",
451 0x140, BIT(31), CLK_SET_RATE_PARENT);
452 static SUNXI_CCU_GATE(ac_dig_4x_clk, "ac-dig-4x", "pll-audio-4x",
453 0x140, BIT(30), CLK_SET_RATE_PARENT);
455 0x144, BIT(31), 0);
457 static const char * const mbus_parents[] = { "osc24M", "pll-periph-2x",
458 "pll-ddr0", "pll-ddr1" };
460 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
462 static const char * const dsi_sclk_parents[] = { "pll-video", "pll-video-2x" };
464 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_sclk_clk, "dsi-sclk",
466 0x168, 16, 4, 24, 2, BIT(31), 0);
468 static const char * const dsi_dphy_parents[] = { "pll-video", "pll-periph" };
470 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy",
472 0x168, 0, 4, 8, 2, BIT(15), 0);
476 0x180, 0, 4, 24, 3, BIT(31), 0);
478 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
479 0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
481 static const char * const ats_parents[] = { "osc24M", "pll-periph" };
483 0x1b0, 0, 3, 24, 2, BIT(31), 0);
588 static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
591 static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
594 static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
597 static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
600 static CLK_FIXED_FACTOR_HW(pll_periph_2x_clk, "pll-periph-2x",
603 static CLK_FIXED_FACTOR_HW(pll_video_2x_clk, "pll-video-2x",
715 [RST_USB_PHY0] = { 0x0cc, BIT(0) },
716 [RST_USB_PHY1] = { 0x0cc, BIT(1) },
717 [RST_USB_HSIC] = { 0x0cc, BIT(2) },
719 [RST_MBUS] = { 0x0fc, BIT(31) },
721 [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) },
722 [RST_BUS_SS] = { 0x2c0, BIT(5) },
723 [RST_BUS_DMA] = { 0x2c0, BIT(6) },
724 [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
725 [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
726 [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
727 [RST_BUS_NAND] = { 0x2c0, BIT(13) },
728 [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
729 [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
730 [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
731 [RST_BUS_SPI1] = { 0x2c0, BIT(21) },
732 [RST_BUS_OTG] = { 0x2c0, BIT(24) },
733 [RST_BUS_EHCI] = { 0x2c0, BIT(26) },
734 [RST_BUS_OHCI] = { 0x2c0, BIT(29) },
736 [RST_BUS_VE] = { 0x2c4, BIT(0) },
737 [RST_BUS_LCD] = { 0x2c4, BIT(4) },
738 [RST_BUS_CSI] = { 0x2c4, BIT(8) },
739 [RST_BUS_DE_BE] = { 0x2c4, BIT(12) },
740 [RST_BUS_DE_FE] = { 0x2c4, BIT(14) },
741 [RST_BUS_GPU] = { 0x2c4, BIT(20) },
742 [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) },
743 [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) },
744 [RST_BUS_DRC] = { 0x2c4, BIT(25) },
745 [RST_BUS_SAT] = { 0x2c4, BIT(26) },
747 [RST_BUS_LVDS] = { 0x2c8, BIT(0) },
749 [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
750 [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
751 [RST_BUS_I2S1] = { 0x2d0, BIT(13) },
753 [RST_BUS_I2C0] = { 0x2d8, BIT(0) },
754 [RST_BUS_I2C1] = { 0x2d8, BIT(1) },
755 [RST_BUS_I2C2] = { 0x2d8, BIT(2) },
756 [RST_BUS_UART0] = { 0x2d8, BIT(16) },
757 [RST_BUS_UART1] = { 0x2d8, BIT(17) },
758 [RST_BUS_UART2] = { 0x2d8, BIT(18) },
759 [RST_BUS_UART3] = { 0x2d8, BIT(19) },
760 [RST_BUS_UART4] = { 0x2d8, BIT(20) },
776 .enable = BIT(31),
777 .lock = BIT(28),
783 .delay_us = 1, /* > 8 clock cycles at 24 MHz */
784 .bypass_index = 1, /* index of 24 MHz oscillator */
798 /* Force the PLL-Audio-1x divider to 1 */ in sun8i_a33_ccu_setup()
803 /* Force PLL-MIPI to MIPI mode */ in sun8i_a33_ccu_setup()
805 val &= ~BIT(16); in sun8i_a33_ccu_setup()
817 CLK_OF_DECLARE(sun8i_a33_ccu, "allwinner,sun8i-a33-ccu",