Lines Matching +full:24 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved.
6 #include <linux/clk-provider.h>
21 #include "ccu-sun9i-a80.h"
28 * Neither mainline Linux, U-boot, nor the vendor BSPs use these.
36 .enable = BIT(31),
37 .lock = BIT(0),
43 .hw.init = CLK_HW_INIT("pll-c0cpux", "osc24M",
50 .enable = BIT(31),
51 .lock = BIT(1),
57 .hw.init = CLK_HW_INIT("pll-c1cpux", "osc24M",
71 .enable = BIT(31),
72 .lock = BIT(2),
79 .hw.init = CLK_HW_INIT("pll-audio", "osc24M",
86 .enable = BIT(31),
87 .lock = BIT(3),
95 .hw.init = CLK_HW_INIT("pll-periph0", "osc24M",
102 .enable = BIT(31),
103 .lock = BIT(4),
111 .hw.init = CLK_HW_INIT("pll-ve", "osc24M",
118 .enable = BIT(31),
119 .lock = BIT(5),
127 .hw.init = CLK_HW_INIT("pll-ddr", "osc24M",
134 .enable = BIT(31),
135 .lock = BIT(6),
142 .hw.init = CLK_HW_INIT("pll-video0", "osc24M",
149 .enable = BIT(31),
150 .lock = BIT(7),
158 .hw.init = CLK_HW_INIT("pll-video1", "osc24M",
165 .enable = BIT(31),
166 .lock = BIT(8),
174 .hw.init = CLK_HW_INIT("pll-gpu", "osc24M",
181 .enable = BIT(31),
182 .lock = BIT(9),
190 .hw.init = CLK_HW_INIT("pll-de", "osc24M",
197 .enable = BIT(31),
198 .lock = BIT(10),
206 .hw.init = CLK_HW_INIT("pll-isp", "osc24M",
213 .enable = BIT(31),
214 .lock = BIT(11),
222 .hw.init = CLK_HW_INIT("pll-periph1", "osc24M",
228 static const char * const c0cpux_parents[] = { "osc24M", "pll-c0cpux" };
232 static const char * const c1cpux_parents[] = { "osc24M", "pll-c1cpux" };
258 static const char * const gtbus_parents[] = { "osc24M", "pll-periph0",
259 "pll-periph1", "pll-periph1" };
261 0x05c, 0, 2, 24, 2, CLK_IS_CRITICAL);
263 static const char * const ahb_parents[] = { "gtbus", "pll-periph0",
264 "pll-periph1", "pll-periph1" };
267 .mux = _SUNXI_CCU_MUX(24, 2),
279 .mux = _SUNXI_CCU_MUX(24, 2),
291 .mux = _SUNXI_CCU_MUX(24, 2),
301 static const char * const apb_parents[] = { "osc24M", "pll-periph0" };
305 .mux = _SUNXI_CCU_MUX(24, 1),
317 .mux = _SUNXI_CCU_MUX(24, 1),
329 .mux = _SUNXI_CCU_MUX(24, 2),
340 0x080, 0, 3, 24, 2, BIT(31), 0);
343 0x084, 0, 3, 24, 2, BIT(31), 0);
351 .enable = BIT(31),
355 .shift = 24,
363 .hw.init = CLK_HW_INIT_PARENTS("out-a",
371 .enable = BIT(31),
375 .shift = 24,
383 .hw.init = CLK_HW_INIT_PARENTS("out-b",
390 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0" };
392 static SUNXI_CCU_MP_WITH_MUX_GATE(nand0_0_clk, "nand0-0", mod0_default_parents,
396 24, 4, /* mux */
397 BIT(31), /* gate */
400 static SUNXI_CCU_MP_WITH_MUX_GATE(nand0_1_clk, "nand0-1", mod0_default_parents,
404 24, 4, /* mux */
405 BIT(31), /* gate */
408 static SUNXI_CCU_MP_WITH_MUX_GATE(nand1_0_clk, "nand1-0", mod0_default_parents,
412 24, 4, /* mux */
413 BIT(31), /* gate */
416 static SUNXI_CCU_MP_WITH_MUX_GATE(nand1_1_clk, "nand1-1", mod0_default_parents,
420 24, 4, /* mux */
421 BIT(31), /* gate */
428 24, 4, /* mux */
429 BIT(31), /* gate */
432 static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0-sample", "mmc0",
434 static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0-output", "mmc0",
441 24, 4, /* mux */
442 BIT(31), /* gate */
445 static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1-sample", "mmc1",
447 static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1-output", "mmc1",
454 24, 4, /* mux */
455 BIT(31), /* gate */
458 static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2-sample", "mmc2",
460 static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2-output", "mmc2",
467 24, 4, /* mux */
468 BIT(31), /* gate */
471 static SUNXI_CCU_PHASE(mmc3_sample_clk, "mmc3-sample", "mmc3",
473 static SUNXI_CCU_PHASE(mmc3_output_clk, "mmc3-output", "mmc3",
480 24, 4, /* mux */
481 BIT(31), /* gate */
484 static const char * const ss_parents[] = { "osc24M", "pll-periph",
485 "pll-periph1" };
488 .enable = BIT(31),
491 .mux = _SUNXI_CCU_MUX_TABLE(24, 4, ss_table),
505 24, 4, /* mux */
506 BIT(31), /* gate */
513 24, 4, /* mux */
514 BIT(31), /* gate */
521 24, 4, /* mux */
522 BIT(31), /* gate */
529 24, 4, /* mux */
530 BIT(31), /* gate */
533 static SUNXI_CCU_M_WITH_GATE(i2s0_clk, "i2s0", "pll-audio",
534 0x440, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
535 static SUNXI_CCU_M_WITH_GATE(i2s1_clk, "i2s1", "pll-audio",
536 0x444, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
537 static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio",
538 0x44c, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
540 static const char * const sdram_parents[] = { "pll-periph0", "pll-ddr" };
551 static SUNXI_CCU_M_WITH_GATE(de_clk, "de", "pll-de", 0x490,
552 0, 4, BIT(31), CLK_SET_RATE_PARENT);
554 static SUNXI_CCU_GATE(edp_clk, "edp", "osc24M", 0x494, BIT(31), 0);
556 static const char * const mp_parents[] = { "pll-video1", "pll-gpu", "pll-de" };
561 24, 4, /* mux */
562 BIT(31), /* gate */
565 static const char * const display_parents[] = { "pll-video0", "pll-video1" };
572 24, 4, /* mux */
573 BIT(31), /* gate */
581 24, 4, /* mux */
582 BIT(31), /* gate */
586 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(mipi_dsi0_clk, "mipi-dsi0",
590 24, 4, /* mux */
591 BIT(31), /* gate */
594 static const char * const mipi_dsi1_parents[] = { "osc24M", "pll-video1" };
596 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(mipi_dsi1_clk, "mipi-dsi1",
600 24, 4, /* mux */
601 BIT(31), /* gate */
608 24, 4, /* mux */
609 BIT(31), /* gate */
613 static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M", 0x4b4, BIT(31), 0);
615 static SUNXI_CCU_M_WITH_GATE(mipi_csi_clk, "mipi-csi", "osc24M", 0x4bc,
616 0, 4, BIT(31), 0);
618 static SUNXI_CCU_M_WITH_GATE(csi_isp_clk, "csi-isp", "pll-isp", 0x4c0,
619 0, 4, BIT(31), CLK_SET_RATE_PARENT);
621 static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M", 0x4c0, BIT(16), 0);
623 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi0_mclk_clk, "csi0-mclk",
627 24, 4, /* mux */
628 BIT(31), /* gate */
631 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi1_mclk_clk, "csi1-mclk",
635 24, 4, /* mux */
636 BIT(31), /* gate */
639 static const char * const fd_parents[] = { "pll-periph0", "pll-isp" };
644 24, 4, /* mux */
645 BIT(31), /* gate */
647 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", 0x4d0,
648 16, 3, BIT(31), CLK_SET_RATE_PARENT);
650 static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 0x4d4, BIT(31), 0);
652 static SUNXI_CCU_M_WITH_GATE(gpu_core_clk, "gpu-core", "pll-gpu", 0x4f0,
653 0, 3, BIT(31), CLK_SET_RATE_PARENT);
654 static SUNXI_CCU_M_WITH_GATE(gpu_memory_clk, "gpu-memory", "pll-gpu", 0x4f4,
655 0, 3, BIT(31), CLK_SET_RATE_PARENT);
657 static const char * const gpu_axi_parents[] = { "pll-periph0", "pll-gpu" };
659 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(gpu_axi_clk, "gpu-axi",
663 24, 4, /* mux */
664 BIT(31), /* gate */
667 static SUNXI_CCU_M_WITH_GATE(sata_clk, "sata", "pll-periph0", 0x500,
668 0, 4, BIT(31), 0);
670 static SUNXI_CCU_M_WITH_GATE(ac97_clk, "ac97", "pll-audio",
671 0x504, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
673 static SUNXI_CCU_M_WITH_MUX_GATE(mipi_hsi_clk, "mipi-hsi",
676 24, 4, /* mux */
677 BIT(31), /* gate */
680 static const char * const gpadc_parents[] = { "osc24M", "pll-audio", "osc32k" };
683 .enable = BIT(31),
686 .mux = _SUNXI_CCU_MUX_TABLE(24, 4, gpadc_table),
699 .enable = BIT(31),
702 .mux = _SUNXI_CCU_MUX_TABLE(24, 4, cir_tx_table),
705 .hw.init = CLK_HW_INIT_PARENTS("cir-tx",
713 static SUNXI_CCU_GATE(bus_fd_clk, "bus-fd", "ahb0",
714 0x580, BIT(0), 0);
715 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb0",
716 0x580, BIT(1), 0);
717 static SUNXI_CCU_GATE(bus_gpu_ctrl_clk, "bus-gpu-ctrl", "ahb0",
718 0x580, BIT(3), 0);
719 static SUNXI_CCU_GATE(bus_ss_clk, "bus-ss", "ahb0",
720 0x580, BIT(5), 0);
721 static SUNXI_CCU_GATE(bus_mmc_clk, "bus-mmc", "ahb0",
722 0x580, BIT(8), 0);
723 static SUNXI_CCU_GATE(bus_nand0_clk, "bus-nand0", "ahb0",
724 0x580, BIT(12), 0);
725 static SUNXI_CCU_GATE(bus_nand1_clk, "bus-nand1", "ahb0",
726 0x580, BIT(13), 0);
727 static SUNXI_CCU_GATE(bus_sdram_clk, "bus-sdram", "ahb0",
728 0x580, BIT(14), 0);
729 static SUNXI_CCU_GATE(bus_mipi_hsi_clk, "bus-mipi-hsi", "ahb0",
730 0x580, BIT(15), 0);
731 static SUNXI_CCU_GATE(bus_sata_clk, "bus-sata", "ahb0",
732 0x580, BIT(16), 0);
733 static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb0",
734 0x580, BIT(18), 0);
735 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb0",
736 0x580, BIT(20), 0);
737 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb0",
738 0x580, BIT(21), 0);
739 static SUNXI_CCU_GATE(bus_spi2_clk, "bus-spi2", "ahb0",
740 0x580, BIT(22), 0);
741 static SUNXI_CCU_GATE(bus_spi3_clk, "bus-spi3", "ahb0",
742 0x580, BIT(23), 0);
745 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
746 0x584, BIT(0), 0);
747 static SUNXI_CCU_GATE(bus_usb_clk, "bus-usb", "ahb1",
748 0x584, BIT(1), 0);
749 static SUNXI_CCU_GATE(bus_gmac_clk, "bus-gmac", "ahb1",
750 0x584, BIT(17), 0);
751 static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",
752 0x584, BIT(21), 0);
753 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
754 0x584, BIT(22), 0);
755 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
756 0x584, BIT(23), 0);
757 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
758 0x584, BIT(24), 0);
761 static SUNXI_CCU_GATE(bus_lcd0_clk, "bus-lcd0", "ahb2",
762 0x588, BIT(0), 0);
763 static SUNXI_CCU_GATE(bus_lcd1_clk, "bus-lcd1", "ahb2",
764 0x588, BIT(1), 0);
765 static SUNXI_CCU_GATE(bus_edp_clk, "bus-edp", "ahb2",
766 0x588, BIT(2), 0);
767 static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb2",
768 0x588, BIT(4), 0);
769 static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb2",
770 0x588, BIT(5), 0);
771 static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb2",
772 0x588, BIT(7), 0);
773 static SUNXI_CCU_GATE(bus_mp_clk, "bus-mp", "ahb2",
774 0x588, BIT(8), 0);
775 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb2",
776 0x588, BIT(11), 0);
779 static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb0",
780 0x590, BIT(1), 0);
781 static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb0",
782 0x590, BIT(5), 0);
783 static SUNXI_CCU_GATE(bus_ac97_clk, "bus-ac97", "apb0",
784 0x590, BIT(11), 0);
785 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb0",
786 0x590, BIT(12), 0);
787 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb0",
788 0x590, BIT(13), 0);
789 static SUNXI_CCU_GATE(bus_lradc_clk, "bus-lradc", "apb0",
790 0x590, BIT(15), 0);
791 static SUNXI_CCU_GATE(bus_gpadc_clk, "bus-gpadc", "apb0",
792 0x590, BIT(17), 0);
793 static SUNXI_CCU_GATE(bus_twd_clk, "bus-twd", "apb0",
794 0x590, BIT(18), 0);
795 static SUNXI_CCU_GATE(bus_cir_tx_clk, "bus-cir-tx", "apb0",
796 0x590, BIT(19), 0);
799 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb1",
800 0x594, BIT(0), 0);
801 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb1",
802 0x594, BIT(1), 0);
803 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb1",
804 0x594, BIT(2), 0);
805 static SUNXI_CCU_GATE(bus_i2c3_clk, "bus-i2c3", "apb1",
806 0x594, BIT(3), 0);
807 static SUNXI_CCU_GATE(bus_i2c4_clk, "bus-i2c4", "apb1",
808 0x594, BIT(4), 0);
809 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb1",
810 0x594, BIT(16), 0);
811 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb1",
812 0x594, BIT(17), 0);
813 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb1",
814 0x594, BIT(18), 0);
815 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb1",
816 0x594, BIT(19), 0);
817 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb1",
818 0x594, BIT(20), 0);
819 static SUNXI_CCU_GATE(bus_uart5_clk, "bus-uart5", "apb1",
820 0x594, BIT(21), 0);
1113 [RST_BUS_FD] = { 0x5a0, BIT(0) },
1114 [RST_BUS_VE] = { 0x5a0, BIT(1) },
1115 [RST_BUS_GPU_CTRL] = { 0x5a0, BIT(3) },
1116 [RST_BUS_SS] = { 0x5a0, BIT(5) },
1117 [RST_BUS_MMC] = { 0x5a0, BIT(8) },
1118 [RST_BUS_NAND0] = { 0x5a0, BIT(12) },
1119 [RST_BUS_NAND1] = { 0x5a0, BIT(13) },
1120 [RST_BUS_SDRAM] = { 0x5a0, BIT(14) },
1121 [RST_BUS_SATA] = { 0x5a0, BIT(16) },
1122 [RST_BUS_TS] = { 0x5a0, BIT(18) },
1123 [RST_BUS_SPI0] = { 0x5a0, BIT(20) },
1124 [RST_BUS_SPI1] = { 0x5a0, BIT(21) },
1125 [RST_BUS_SPI2] = { 0x5a0, BIT(22) },
1126 [RST_BUS_SPI3] = { 0x5a0, BIT(23) },
1129 [RST_BUS_OTG] = { 0x5a4, BIT(0) },
1130 [RST_BUS_OTG_PHY] = { 0x5a4, BIT(1) },
1131 [RST_BUS_MIPI_HSI] = { 0x5a4, BIT(9) },
1132 [RST_BUS_GMAC] = { 0x5a4, BIT(17) },
1133 [RST_BUS_MSGBOX] = { 0x5a4, BIT(21) },
1134 [RST_BUS_SPINLOCK] = { 0x5a4, BIT(22) },
1135 [RST_BUS_HSTIMER] = { 0x5a4, BIT(23) },
1136 [RST_BUS_DMA] = { 0x5a4, BIT(24) },
1139 [RST_BUS_LCD0] = { 0x5a8, BIT(0) },
1140 [RST_BUS_LCD1] = { 0x5a8, BIT(1) },
1141 [RST_BUS_EDP] = { 0x5a8, BIT(2) },
1142 [RST_BUS_LVDS] = { 0x5a8, BIT(3) },
1143 [RST_BUS_CSI] = { 0x5a8, BIT(4) },
1144 [RST_BUS_HDMI0] = { 0x5a8, BIT(5) },
1145 [RST_BUS_HDMI1] = { 0x5a8, BIT(6) },
1146 [RST_BUS_DE] = { 0x5a8, BIT(7) },
1147 [RST_BUS_MP] = { 0x5a8, BIT(8) },
1148 [RST_BUS_GPU] = { 0x5a8, BIT(9) },
1149 [RST_BUS_MIPI_DSI] = { 0x5a8, BIT(11) },
1152 [RST_BUS_SPDIF] = { 0x5b0, BIT(1) },
1153 [RST_BUS_AC97] = { 0x5b0, BIT(11) },
1154 [RST_BUS_I2S0] = { 0x5b0, BIT(12) },
1155 [RST_BUS_I2S1] = { 0x5b0, BIT(13) },
1156 [RST_BUS_LRADC] = { 0x5b0, BIT(15) },
1157 [RST_BUS_GPADC] = { 0x5b0, BIT(17) },
1158 [RST_BUS_CIR_TX] = { 0x5b0, BIT(19) },
1161 [RST_BUS_I2C0] = { 0x5b4, BIT(0) },
1162 [RST_BUS_I2C1] = { 0x5b4, BIT(1) },
1163 [RST_BUS_I2C2] = { 0x5b4, BIT(2) },
1164 [RST_BUS_I2C3] = { 0x5b4, BIT(3) },
1165 [RST_BUS_I2C4] = { 0x5b4, BIT(4) },
1166 [RST_BUS_UART0] = { 0x5b4, BIT(16) },
1167 [RST_BUS_UART1] = { 0x5b4, BIT(17) },
1168 [RST_BUS_UART2] = { 0x5b4, BIT(18) },
1169 [RST_BUS_UART3] = { 0x5b4, BIT(19) },
1170 [RST_BUS_UART4] = { 0x5b4, BIT(20) },
1171 [RST_BUS_UART5] = { 0x5b4, BIT(21) },
1193 if (!(val & BIT(SUN9I_A80_PLL_P_SHIFT))) in sun9i_a80_cpu_pll_fixup()
1204 val &= ~GENMASK(SUN9I_A80_PLL_N_SHIFT + SUN9I_A80_PLL_N_WIDTH - 1, in sun9i_a80_cpu_pll_fixup()
1209 val &= ~BIT(SUN9I_A80_PLL_P_SHIFT); in sun9i_a80_cpu_pll_fixup()
1221 reg = devm_ioremap_resource(&pdev->dev, res); in sun9i_a80_ccu_probe()
1227 val &= ~(BIT(16) | BIT(18)); in sun9i_a80_ccu_probe()
1234 return sunxi_ccu_probe(pdev->dev.of_node, reg, &sun9i_a80_ccu_desc); in sun9i_a80_ccu_probe()
1238 { .compatible = "allwinner,sun9i-a80-ccu" },
1245 .name = "sun9i-a80-ccu",