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/Linux-v6.1/Documentation/devicetree/bindings/media/i2c/
Dtda1997x.txt1 Device-Tree bindings for the NXP TDA1997x HDMI receiver
6 - RGB 8bit per color (24 bits total): R[11:4] B[11:4] G[11:4]
7 - YUV444 8bit per color (24 bits total): Y[11:4] Cr[11:4] Cb[11:4]
8 - YUV422 semi-planar 8bit per component (16 bits total): Y[11:4] CbCr[11:4]
9 - YUV422 semi-planar 10bit per component (20 bits total): Y[11:2] CbCr[11:2]
10 - YUV422 semi-planar 12bit per component (24 bits total): - Y[11:0] CbCr[11:0]
11 - YUV422 BT656 8bit per component (8 bits total): YCbCr[11:4] (2-cycles)
12 - YUV422 BT656 10bit per component (10 bits total): YCbCr[11:2] (2-cycles)
13 - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
16 - RGB 12bit per color (36 bits total): R[11:0] B[11:0] G[11:0]
[all …]
/Linux-v6.1/drivers/net/wireless/mediatek/mt76/mt7615/
Dmac.h1 /* SPDX-License-Identifier: ISC */
15 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
16 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
17 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
18 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
19 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
20 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
37 #define MT_RXD1_MID_AMSDU_FRAME BIT(1)
38 #define MT_RXD1_LAST_AMSDU_FRAME BIT(0)
39 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
[all …]
/Linux-v6.1/include/soc/mscc/
Docelot_hsio.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
85 #define HSIO_PLL5G_CFG0_ENA_ROT BIT(31)
86 #define HSIO_PLL5G_CFG0_ENA_LANE BIT(30)
87 #define HSIO_PLL5G_CFG0_ENA_CLKTREE BIT(29)
88 #define HSIO_PLL5G_CFG0_DIV4 BIT(28)
89 #define HSIO_PLL5G_CFG0_ENA_LOCK_FINE BIT(27)
99 #define HSIO_PLL5G_CFG0_ENA_VCO_CONTRH BIT(15)
100 #define HSIO_PLL5G_CFG0_ENA_CP1 BIT(14)
101 #define HSIO_PLL5G_CFG0_ENA_VCO_BUF BIT(13)
102 #define HSIO_PLL5G_CFG0_ENA_BIAS BIT(12)
[all …]
Docelot_ana.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
11 #define ANA_ANAGEFIL_B_DOM_EN BIT(22)
12 #define ANA_ANAGEFIL_B_DOM_VAL BIT(21)
13 #define ANA_ANAGEFIL_AGE_LOCKED BIT(20)
14 #define ANA_ANAGEFIL_PID_EN BIT(19)
18 #define ANA_ANAGEFIL_VID_EN BIT(13)
27 #define ANA_STORMLIMIT_CFG_STORM_UNIT BIT(2)
31 #define ANA_AUTOAGE_AGE_FAST BIT(21)
35 #define ANA_AUTOAGE_AUTOAGE_LOCKED BIT(0)
37 #define ANA_MACTOPTIONS_REDUCED_TABLE BIT(1)
[all …]
/Linux-v6.1/include/linux/soc/mediatek/
Dinfracfg.h1 /* SPDX-License-Identifier: GPL-2.0 */
33 #define MT8195_TOP_AXI_PROT_EN_VDOSYS0 BIT(6)
34 #define MT8195_TOP_AXI_PROT_EN_VPPSYS0 BIT(10)
35 #define MT8195_TOP_AXI_PROT_EN_MFG1 BIT(11)
37 #define MT8195_TOP_AXI_PROT_EN_VPPSYS0_2ND BIT(23)
39 #define MT8195_TOP_AXI_PROT_EN_1_CAM BIT(22)
40 #define MT8195_TOP_AXI_PROT_EN_2_CAM BIT(0)
42 #define MT8195_TOP_AXI_PROT_EN_2_MFG1 BIT(7)
43 #define MT8195_TOP_AXI_PROT_EN_2_AUDIO (BIT(9) | BIT(11))
44 #define MT8195_TOP_AXI_PROT_EN_2_ADSP (BIT(12) | GENMASK(16, 14))
[all …]
/Linux-v6.1/drivers/net/can/ctucanfd/
Dctucanfd_kregs.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Copyright (C) 2015-2018 Ondrej Ille <ondrej.ille@gmail.com> FEE CTU
7 * Copyright (C) 2018-2022 Ondrej Ille <ondrej.ille@gmail.com> self-funded
8 * Copyright (C) 2018-2019 Martin Jerabek <martin.jerabek01@gmail.com> FEE CTU
9 * Copyright (C) 2018-2022 Pavel Pisa <pisa@cmp.felk.cvut.cz> FEE CTU/self-funded
103 #define REG_MODE_RST BIT(0)
104 #define REG_MODE_BMM BIT(1)
105 #define REG_MODE_STM BIT(2)
106 #define REG_MODE_AFM BIT(3)
107 #define REG_MODE_FDE BIT(4)
[all …]
/Linux-v6.1/drivers/net/wireless/mediatek/mt76/mt7603/
Dmac.h1 /* SPDX-License-Identifier: ISC */
10 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
11 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
12 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
13 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
14 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
15 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
29 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
30 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)
34 #define MT_RXD1_NORMAL_BEACON_UC BIT(5)
[all …]
Dregs.h1 /* SPDX-License-Identifier: ISC */
28 #define MT_INT_RX_DONE(_n) BIT(_n)
31 #define MT_INT_TX_DONE(_n) BIT((_n) + 4)
33 #define MT_INT_RX_COHERENT BIT(20)
34 #define MT_INT_TX_COHERENT BIT(21)
35 #define MT_INT_MAC_IRQ3 BIT(27)
37 #define MT_INT_MCU_CMD BIT(30)
40 #define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0)
41 #define MT_WPDMA_GLO_CFG_TX_DMA_BUSY BIT(1)
42 #define MT_WPDMA_GLO_CFG_RX_DMA_EN BIT(2)
[all …]
/Linux-v6.1/drivers/net/ethernet/asix/
Dax88796c_main.h1 /* SPDX-License-Identifier: GPL-2.0-only */
121 #define AX_FC_RX BIT(0)
122 #define AX_FC_TX BIT(1)
123 #define AX_FC_ANEG BIT(2)
126 #define AX_CAP_COMP BIT(0)
153 #define PSR_DEV_READY BIT(7)
155 #define PSR_RESET_CLR BIT(15)
158 #define FER_IPALM BIT(0)
159 #define FER_DCRC BIT(1)
160 #define FER_RH3M BIT(2)
[all …]
/Linux-v6.1/drivers/net/wireless/realtek/rtw89/
Dreg.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
9 #define B_AX_AUTOLOAD_SUS BIT(5)
13 #define B_AX_PWC_EV2EF_B15 BIT(15)
14 #define B_AX_PWC_EV2EF_B14 BIT(14)
15 #define B_AX_ISO_EB2CORE BIT(8)
18 #define B_AX_FEN_BB_GLB_RSTN BIT(1)
19 #define B_AX_FEN_BBRSTB BIT(0)
22 #define B_AX_XTAL_OFF_A_DIE BIT(22)
23 #define B_AX_DIS_WLBT_PDNSUSEN_SOPC BIT(18)
[all …]
/Linux-v6.1/drivers/net/ethernet/stmicro/stmmac/
Ddescs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
18 #define RDES0_PAYLOAD_CSUM_ERR BIT(0)
19 #define RDES0_CRC_ERROR BIT(1)
20 #define RDES0_DRIBBLING BIT(2)
21 #define RDES0_MII_ERROR BIT(3)
22 #define RDES0_RECEIVE_WATCHDOG BIT(4)
23 #define RDES0_FRAME_TYPE BIT(5)
24 #define RDES0_COLLISION BIT(6)
25 #define RDES0_IPC_CSUM_ERROR BIT(7)
26 #define RDES0_LAST_DESCRIPTOR BIT(8)
[all …]
/Linux-v6.1/drivers/comedi/drivers/
Dni_stc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Register descriptions for NI DAQ-STC chip
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 1998-9 David A. Schleef <ds@schleef.org>
11 * DAQ-STC Technical Reference Manual
21 * Registers in the National Instruments DAQ-STC chip
25 #define NISTC_INTA_ACK_G0_GATE BIT(15)
26 #define NISTC_INTA_ACK_G0_TC BIT(14)
27 #define NISTC_INTA_ACK_AI_ERR BIT(13)
28 #define NISTC_INTA_ACK_AI_STOP BIT(12)
[all …]
/Linux-v6.1/drivers/gpu/drm/mcde/
Dmcde_display_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 #define MCDE_PP_VCMPA BIT(0)
12 #define MCDE_PP_VCMPB BIT(1)
13 #define MCDE_PP_VSCC0 BIT(2)
14 #define MCDE_PP_VSCC1 BIT(3)
15 #define MCDE_PP_VCMPC0 BIT(4)
16 #define MCDE_PP_VCMPC1 BIT(5)
17 #define MCDE_PP_ROTFD_A BIT(6)
18 #define MCDE_PP_ROTFD_B BIT(7)
74 #define MCDE_EXTSRCXCONF_BPP_YCBCR422 11
[all …]
/Linux-v6.1/drivers/mmc/host/
Dmeson-mx-sdhc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
15 #define MESON_SDHC_SEND_CMD_HAS_RESP BIT(6)
16 #define MESON_SDHC_SEND_CMD_HAS_DATA BIT(7)
17 #define MESON_SDHC_SEND_RESP_LEN BIT(8)
18 #define MESON_SDHC_SEND_RESP_NO_CRC BIT(9)
19 #define MESON_SDHC_SEND_DATA_DIR BIT(10)
20 #define MESON_SDHC_SEND_DATA_STOP BIT(11)
21 #define MESON_SDHC_SEND_R1B BIT(12)
26 #define MESON_SDHC_CTRL_DDR_MODE BIT(2)
27 #define MESON_SDHC_CTRL_TX_CRC_NOCHECK BIT(3)
[all …]
/Linux-v6.1/drivers/power/supply/
Dbd99954-charger.h1 /* SPDX-License-Identifier: GPL-2.0-only */
500 [F_PP_BOTH_THRU] = REG_FIELD(VIN_CTRL_SET, 11, 11),
510 [F_VCC_BC_DISEN] = REG_FIELD(CHGOP_SET1, 11, 11),
550 [F_PROCHOT_ICRIT_DG_SET] = REG_FIELD(PROCHOT_CTRL_SET, 10, 11),
565 [F_IOUT_DACIN_VAL] = REG_FIELD(IOUT_DACIN_VAL, 0, 11),
577 [F_VCC_PUPDET] = REG_FIELD(VCC_UCD_STATUS, 11, 11),
621 [F_VBUS_PUPDET] = REG_FIELD(VBUS_UCD_STATUS, 11, 11),
657 [F_ONE_CELL_MODE] = REG_FIELD(IC_SET1, 11, 11),
674 [F_ADCTMOD] = REG_FIELD(VM_CTRL_SET, 10, 11),
704 [F_EXTIADP_TH_SET] = REG_FIELD(EXTIADP_TH_SET, 0, 11),
[all …]
/Linux-v6.1/drivers/net/wireless/mediatek/mt76/
Dmt76_connac2_mac.h1 /* SPDX-License-Identifier: ISC */
40 #define MT_TXD1_LONG_FORMAT BIT(31)
41 #define MT_TXD1_TGID BIT(30)
43 #define MT_TXD1_AMSDU BIT(23)
47 #define MT_TXD1_HDR_INFO GENMASK(15, 11)
48 #define MT_TXD1_ETH_802_3 BIT(15)
49 #define MT_TXD1_VTA BIT(10)
52 #define MT_TXD2_FIX_RATE BIT(31)
53 #define MT_TXD2_FIXED_RATE BIT(30)
57 #define MT_TXD2_HTC_VLD BIT(13)
[all …]
/Linux-v6.1/drivers/staging/sm750fb/
Dddk750_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 #define DE_STATE1_DE_ABORT BIT(0)
10 #define DE_STATE2_DE_FIFO_EMPTY BIT(3)
11 #define DE_STATE2_DE_STATUS_BUSY BIT(2)
12 #define DE_STATE2_DE_MEM_FIFO_EMPTY BIT(1)
20 #define SYSTEM_CTRL_PCI_BURST BIT(29)
21 #define SYSTEM_CTRL_PCI_MASTER BIT(25)
22 #define SYSTEM_CTRL_LATENCY_TIMER_OFF BIT(24)
23 #define SYSTEM_CTRL_DE_FIFO_EMPTY BIT(23)
24 #define SYSTEM_CTRL_DE_STATUS_BUSY BIT(22)
[all …]
/Linux-v6.1/drivers/clk/stm32/
Dstm32mp13_rcc.h1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
3 * Copyright (C) 2020, STMicroelectronics - All Rights Reserved
222 #define RCC_SECCFGR_MPUSEC 11
238 #define RCC_MP_SREQSETR_STPREQ_P0 BIT(0)
241 #define RCC_MP_SREQCLRR_STPREQ_P0 BIT(0)
244 #define RCC_MP_APRSTCR_RDCTLEN BIT(0)
257 #define RCC_MP_GRSTCSETR_MPSYSRST BIT(0)
258 #define RCC_MP_GRSTCSETR_MPUP0RST BIT(4)
261 #define RCC_BR_RSTSCLRR_PORRSTF BIT(0)
262 #define RCC_BR_RSTSCLRR_BORRSTF BIT(1)
[all …]
/Linux-v6.1/drivers/thunderbolt/
Dtb_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Thunderbolt driver - Port/Switch config area registers
65 * struct tb_cap_extended_short - Switch extended short capability
80 * struct tb_cap_extended_long - Switch extended long capability
98 * struct tb_cap_any - Structure capable of hold every capability
130 u32 unknown3:11;
136 bool fl_sk:1; /* send pulse to transfer one bit */
155 u32 __unknown5[7]; /* VSC_CS_5 -> VSC_CS_11 */
156 u32 drom_offset; /* VSC_CS_12: 32 bit register, but eeprom addresses are 16 bit */
195 #define ROUTER_CS_5_SLP BIT(0)
[all …]
/Linux-v6.1/drivers/net/dsa/b53/
Db53_serdes.h1 /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
11 /* Non-standard page used to access SerDes PHY registers on NorthStar Plus */
18 #define SERDES_ID0_REV_NUM_SHIFT 11
27 #define FIBER_MODE_1000X BIT(0)
28 #define TBI_INTERFACE BIT(1)
29 #define SIGNAL_DETECT_EN BIT(2)
30 #define INVERT_SIGNAL_DETECT BIT(3)
31 #define AUTODET_EN BIT(4)
32 #define SGMII_MASTER_MODE BIT(5)
33 #define DISABLE_DLL_PWRDOWN BIT(6)
[all …]
/Linux-v6.1/drivers/staging/media/atomisp/pci/css_2401_system/hrt/
Dmipi_backend_common_defs.h1 /* SPDX-License-Identifier: GPL-2.0 */
28 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8 24 /* 01 1000 YUV420 8-bit …
29 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_10 25 /* 01 1001 YUV420 10-bit …
30 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8L 26 /* 01 1010 YUV420 8-bit lega…
31 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV422_8 30 /* 01 1110 YUV422 8-bit …
32 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV422_10 31 /* 01 1111 YUV422 10-bit …
44 …CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_1 48 /* 11 0000 JPEG [User Defined 8-bit Dat…
45 …RT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_2 49 /* 11 0001 User Defined 8-bit Data T…
46 …RT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_3 50 /* 11 0010 User Defined 8-bit Data T…
47 …RT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_4 51 /* 11 0011 User Defined 8-bit Data T…
[all …]
/Linux-v6.1/include/linux/amba/
Dpl080.h1 /* SPDX-License-Identifier: GPL-2.0-only */
17 * the ability to move more than 2^11 counts of data and some extra
38 #define PL080_CONFIG_M2_BE BIT(2)
39 #define PL080_CONFIG_M1_BE BIT(1)
40 #define PL080_CONFIG_ENABLE BIT(0)
72 #define PL080_LLI_LM_AHB2 BIT(0)
74 #define PL080_CONTROL_TC_IRQ_EN BIT(31)
77 #define PL080_CONTROL_PROT_CACHE BIT(30)
78 #define PL080_CONTROL_PROT_BUFF BIT(29)
79 #define PL080_CONTROL_PROT_SYS BIT(28)
[all …]
/Linux-v6.1/drivers/gpu/drm/v3d/
Dv3d_regs.h1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2017-2018 Broadcom */
30 # define V3D_HUB_IDENT1_WITH_MSO BIT(19)
31 # define V3D_HUB_IDENT1_WITH_TSY BIT(18)
32 # define V3D_HUB_IDENT1_WITH_TFU BIT(17)
33 # define V3D_HUB_IDENT1_WITH_L3C BIT(16)
36 # define V3D_HUB_IDENT1_NCORES_MASK V3D_MASK(11, 8)
44 # define V3D_HUB_IDENT2_WITH_MMU BIT(8)
60 # define V3D_HUB_INT_MMU_WRV BIT(5)
61 # define V3D_HUB_INT_MMU_PTI BIT(4)
[all …]
/Linux-v6.1/include/linux/
Dfsl-diu-fb.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
7 * Authors: Hongjun Chen <hong-jun.chen@freescale.com>
68 /* Word 0(32-bit) in DDR memory */
81 /* Word 1(32-bit) in DDR memory */
84 /* Word 2(32-bit) in DDR memory */
85 /* __u32 delta_xs:11; */
87 /* __u32 delta_ys:11; */
92 /* Word 3(32-bit) in DDR memory */
93 /* __u32 delta_xi:11; */
95 /* __u32 delta_yi:11; */
[all …]
/Linux-v6.1/drivers/net/ethernet/marvell/
Dskge.h1 /* SPDX-License-Identifier: GPL-2.0 */
131 /* B0_CTST 16 bit Control/Status register */
133 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
134 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
138 CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
142 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
148 /* B0_LED 8 Bit LED register */
149 /* Bit 7.. 2: reserved */
153 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
[all …]

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