Lines Matching +full:11 +full:- +full:bit
1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
11 #define ANA_ANAGEFIL_B_DOM_EN BIT(22)
12 #define ANA_ANAGEFIL_B_DOM_VAL BIT(21)
13 #define ANA_ANAGEFIL_AGE_LOCKED BIT(20)
14 #define ANA_ANAGEFIL_PID_EN BIT(19)
18 #define ANA_ANAGEFIL_VID_EN BIT(13)
27 #define ANA_STORMLIMIT_CFG_STORM_UNIT BIT(2)
31 #define ANA_AUTOAGE_AGE_FAST BIT(21)
35 #define ANA_AUTOAGE_AUTOAGE_LOCKED BIT(0)
37 #define ANA_MACTOPTIONS_REDUCED_TABLE BIT(1)
38 #define ANA_MACTOPTIONS_SHADOW BIT(0)
43 #define ANA_AGENCTRL_IGNORE_DMAC_FLAGS BIT(11)
44 #define ANA_AGENCTRL_IGNORE_SMAC_FLAGS BIT(10)
45 #define ANA_AGENCTRL_FLOOD_SPECIAL BIT(9)
46 #define ANA_AGENCTRL_FLOOD_IGNORE_VLAN BIT(8)
47 #define ANA_AGENCTRL_MIRROR_CPU BIT(7)
48 #define ANA_AGENCTRL_LEARN_CPU_COPY BIT(6)
49 #define ANA_AGENCTRL_LEARN_FWD_KILL BIT(5)
50 #define ANA_AGENCTRL_LEARN_IGNORE_VLAN BIT(4)
51 #define ANA_AGENCTRL_CPU_CPU_KILL_ENA BIT(3)
52 #define ANA_AGENCTRL_GREEN_COUNT_MODE BIT(2)
53 #define ANA_AGENCTRL_YELLOW_COUNT_MODE BIT(1)
54 #define ANA_AGENCTRL_RED_COUNT_MODE BIT(0)
61 #define ANA_FLOODING_FLD_BROADCAST(x) (((x) << 6) & GENMASK(11, 6))
62 #define ANA_FLOODING_FLD_BROADCAST_M GENMASK(11, 6)
63 #define ANA_FLOODING_FLD_BROADCAST_X(x) (((x) & GENMASK(11, 6)) >> 6)
73 #define ANA_FLOODING_IPMC_FLD_MC6_CTRL(x) (((x) << 6) & GENMASK(11, 6))
74 #define ANA_FLOODING_IPMC_FLD_MC6_CTRL_M GENMASK(11, 6)
75 #define ANA_FLOODING_IPMC_FLD_MC6_CTRL_X(x) (((x) & GENMASK(11, 6)) >> 6)
84 #define ANA_SFLOW_CFG_SF_SAMPLE_RX BIT(1)
85 #define ANA_SFLOW_CFG_SF_SAMPLE_TX BIT(0)
89 #define ANA_PORT_MODE_REDTAG_PARSE_CFG BIT(3)
93 #define ANA_PORT_MODE_L3_PARSE_CFG BIT(0)
99 #define ANA_PGID_PGID_PGID(x) ((x) & GENMASK(11, 0))
100 #define ANA_PGID_PGID_PGID_M GENMASK(11, 0)
111 #define ANA_TABLES_STREAMDATA_SSID_VALID BIT(16)
115 #define ANA_TABLES_STREAMDATA_SFID_VALID BIT(8)
119 #define ANA_TABLES_MACACCESS_MAC_CPU_COPY BIT(15)
120 #define ANA_TABLES_MACACCESS_SRC_KILL BIT(14)
121 #define ANA_TABLES_MACACCESS_IGNORE_VLAN BIT(13)
122 #define ANA_TABLES_MACACCESS_AGED_FLAG BIT(12)
123 #define ANA_TABLES_MACACCESS_VALID BIT(11)
150 #define ANA_TABLES_VLANTIDX_VLAN_SEC_FWD_ENA BIT(17)
151 #define ANA_TABLES_VLANTIDX_VLAN_FLOOD_DIS BIT(16)
152 #define ANA_TABLES_VLANTIDX_VLAN_PRIV_VLAN BIT(15)
153 #define ANA_TABLES_VLANTIDX_VLAN_LEARN_DISABLED BIT(14)
154 #define ANA_TABLES_VLANTIDX_VLAN_MIRROR BIT(13)
155 #define ANA_TABLES_VLANTIDX_VLAN_SRC_CHK BIT(12)
156 #define ANA_TABLES_VLANTIDX_V_INDEX(x) ((x) & GENMASK(11, 0))
157 #define ANA_TABLES_VLANTIDX_V_INDEX_M GENMASK(11, 0)
171 #define ANA_TABLES_ISDXTIDX_ISDX_ES0_KEY_ENA BIT(14)
172 #define ANA_TABLES_ISDXTIDX_ISDX_FORCE_ENA BIT(10)
187 #define ANA_TABLES_STREAMACCESS_SEQ_GEN_REC_ENA BIT(3)
188 #define ANA_TABLES_STREAMACCESS_GEN_REC_TYPE BIT(2)
198 #define ANA_TABLES_STREAMTIDX_FORCE_SF_BEHAVIOUR BIT(14)
202 #define ANA_TABLES_STREAMTIDX_RESET_ON_ROGUE BIT(7)
203 #define ANA_TABLES_STREAMTIDX_REDTAG_POP BIT(6)
204 #define ANA_TABLES_STREAMTIDX_STREAM_SPLIT BIT(5)
217 #define ANA_TABLES_SFID_MASK_IGR_SRCPORT_MATCH_ENA BIT(0)
219 #define ANA_TABLES_SFIDACCESS_IGR_PRIO_MATCH_ENA BIT(22)
223 #define ANA_TABLES_SFIDACCESS_FORCE_BLOCK BIT(18)
235 #define ANA_TABLES_SFIDTIDX_SGID_VALID BIT(26)
239 #define ANA_TABLES_SFIDTIDX_POL_ENA BIT(17)
252 #define ANA_SG_ACCESS_CTRL_CONFIG_CHANGE BIT(28)
259 #define ANA_SG_CONFIG_REG_3_GATE_ENABLE BIT(20)
263 #define ANA_SG_CONFIG_REG_3_IPV_VALID BIT(24)
268 #define ANA_SG_CONFIG_REG_3_INIT_GATE_STATE BIT(25)
274 #define ANA_SG_GCL_GS_CONFIG_GATE_STATE BIT(4)
280 #define ANA_SG_STATUS_REG_3_GATE_STATE BIT(16)
284 #define ANA_SG_STATUS_REG_3_CONFIG_PENDING BIT(24)
288 #define ANA_PORT_VLAN_CFG_VLAN_VID_AS_ISDX BIT(21)
289 #define ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA BIT(20)
293 #define ANA_PORT_VLAN_CFG_VLAN_INNER_TAG_ENA BIT(17)
294 #define ANA_PORT_VLAN_CFG_VLAN_TAG_TYPE BIT(16)
295 #define ANA_PORT_VLAN_CFG_VLAN_DEI BIT(15)
299 #define ANA_PORT_VLAN_CFG_VLAN_VID(x) ((x) & GENMASK(11, 0))
300 #define ANA_PORT_VLAN_CFG_VLAN_VID_M GENMASK(11, 0)
304 #define ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA BIT(6)
305 #define ANA_PORT_DROP_CFG_DROP_S_TAGGED_ENA BIT(5)
306 #define ANA_PORT_DROP_CFG_DROP_C_TAGGED_ENA BIT(4)
307 #define ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA BIT(3)
308 #define ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA BIT(2)
309 #define ANA_PORT_DROP_CFG_DROP_NULL_MAC_ENA BIT(1)
310 #define ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA BIT(0)
314 #define ANA_PORT_QOS_CFG_DP_DEFAULT_VAL BIT(8)
318 #define ANA_PORT_QOS_CFG_QOS_DSCP_ENA BIT(4)
319 #define ANA_PORT_QOS_CFG_QOS_PCP_ENA BIT(3)
320 #define ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA BIT(2)
326 #define ANA_PORT_VCAP_CFG_S1_ENA BIT(14)
327 #define ANA_PORT_VCAP_CFG_S1_DMAC_DIP_ENA(x) (((x) << 11) & GENMASK(13, 11))
328 #define ANA_PORT_VCAP_CFG_S1_DMAC_DIP_ENA_M GENMASK(13, 11)
329 #define ANA_PORT_VCAP_CFG_S1_DMAC_DIP_ENA_X(x) (((x) & GENMASK(13, 11)) >> 11)
356 #define ANA_PORT_VCAP_S2_CFG_S2_ENA BIT(14)
360 #define ANA_PORT_VCAP_S2_CFG_S2_ARP_DIS(x) (((x) << 10) & GENMASK(11, 10))
361 #define ANA_PORT_VCAP_S2_CFG_S2_ARP_DIS_M GENMASK(11, 10)
362 #define ANA_PORT_VCAP_S2_CFG_S2_ARP_DIS_X(x) (((x) & GENMASK(11, 10)) >> 10)
378 #define ANA_PORT_PCP_DEI_MAP_DP_PCP_DEI_VAL BIT(3)
384 #define ANA_PORT_CPU_FWD_CFG_CPU_VRAP_REDIR_ENA BIT(7)
385 #define ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA BIT(6)
386 #define ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA BIT(5)
387 #define ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA BIT(4)
388 #define ANA_PORT_CPU_FWD_CFG_CPU_SRC_COPY_ENA BIT(3)
389 #define ANA_PORT_CPU_FWD_CFG_CPU_ALLBRIDGE_DROP_ENA BIT(2)
390 #define ANA_PORT_CPU_FWD_CFG_CPU_ALLBRIDGE_REDIR_ENA BIT(1)
391 #define ANA_PORT_CPU_FWD_CFG_CPU_OAM_ENA BIT(0)
419 #define ANA_PORT_PORT_CFG_SRC_MIRROR_ENA BIT(15)
420 #define ANA_PORT_PORT_CFG_LIMIT_DROP BIT(14)
421 #define ANA_PORT_PORT_CFG_LIMIT_CPU BIT(13)
422 #define ANA_PORT_PORT_CFG_LOCKED_PORTMOVE_DROP BIT(12)
423 #define ANA_PORT_PORT_CFG_LOCKED_PORTMOVE_CPU BIT(11)
424 #define ANA_PORT_PORT_CFG_LEARNDROP BIT(10)
425 #define ANA_PORT_PORT_CFG_LEARNCPU BIT(9)
426 #define ANA_PORT_PORT_CFG_LEARNAUTO BIT(8)
427 #define ANA_PORT_PORT_CFG_LEARN_ENA BIT(7)
428 #define ANA_PORT_PORT_CFG_RECV_ENA BIT(6)
432 #define ANA_PORT_PORT_CFG_USE_B_DOM_TBL BIT(1)
433 #define ANA_PORT_PORT_CFG_LSR_MODE BIT(0)
437 #define ANA_PORT_POL_CFG_POL_CPU_REDIR_8021 BIT(19)
438 #define ANA_PORT_POL_CFG_POL_CPU_REDIR_IP BIT(18)
439 #define ANA_PORT_POL_CFG_PORT_POL_ENA BIT(17)
448 #define ANA_PORT_PTP_CFG_PTP_BACKPLANE_MODE BIT(0)
457 #define ANA_PORT_SFID_CFG_SFID_VALID BIT(8)
480 #define ANA_IPT_OAM_MEP_CFG_MEP_IDX_ENA BIT(0)
497 #define ANA_FID_MAP_FID_MAP_FID_C_VAL(x) (((x) << 6) & GENMASK(11, 6))
498 #define ANA_FID_MAP_FID_MAP_FID_C_VAL_M GENMASK(11, 6)
499 #define ANA_FID_MAP_FID_MAP_FID_C_VAL_X(x) (((x) & GENMASK(11, 6)) >> 6)
503 #define ANA_AGGR_CFG_AC_RND_ENA BIT(7)
504 #define ANA_AGGR_CFG_AC_DMAC_ENA BIT(6)
505 #define ANA_AGGR_CFG_AC_SMAC_ENA BIT(5)
506 #define ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA BIT(4)
507 #define ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA BIT(3)
508 #define ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA BIT(2)
509 #define ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA BIT(1)
510 #define ANA_AGGR_CFG_AC_ISDX_ENA BIT(0)
530 #define ANA_CPUQ_CFG_CPUQ_MAC_COPY(x) (((x) << 9) & GENMASK(11, 9))
531 #define ANA_CPUQ_CFG_CPUQ_MAC_COPY_M GENMASK(11, 9)
532 #define ANA_CPUQ_CFG_CPUQ_MAC_COPY_X(x) (((x) & GENMASK(11, 9)) >> 9)
555 #define ANA_DSCP_CFG_DP_DSCP_VAL BIT(11)
562 #define ANA_DSCP_CFG_DSCP_TRUST_ENA BIT(1)
563 #define ANA_DSCP_CFG_DSCP_REWR_ENA BIT(0)
577 #define ANA_VRAP_CFG_VRAP_VLAN_AWARE_ENA BIT(12)
578 #define ANA_VRAP_CFG_VRAP_VID(x) ((x) & GENMASK(11, 0))
579 #define ANA_VRAP_CFG_VRAP_VID_M GENMASK(11, 0)
581 #define ANA_DISCARD_CFG_DROP_TAGGING_ISDX0 BIT(3)
582 #define ANA_DISCARD_CFG_DROP_CTRLPROT_ISDX0 BIT(2)
583 #define ANA_DISCARD_CFG_DROP_TAGGING_S2_ENA BIT(1)
584 #define ANA_DISCARD_CFG_DROP_CTRLPROT_S2_ENA BIT(0)
586 #define ANA_FID_CFG_VID_MC_ENA BIT(0)
612 #define ANA_POL_MODE_CFG_DLB_COUPLED BIT(2)
613 #define ANA_POL_MODE_CFG_CIR_ENA BIT(1)
614 #define ANA_POL_MODE_CFG_OVERSHOOT_ENA BIT(0)
624 #define ANA_POL_FLOWC_POL_FLOWC BIT(0)
632 #define ANA_POL_MISC_CFG_POL_CLOSE_ALL BIT(1)
633 #define ANA_POL_MISC_CFG_POL_LEAK_DIS BIT(0)