Lines Matching +full:11 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0+ */
15 #define MESON_SDHC_SEND_CMD_HAS_RESP BIT(6)
16 #define MESON_SDHC_SEND_CMD_HAS_DATA BIT(7)
17 #define MESON_SDHC_SEND_RESP_LEN BIT(8)
18 #define MESON_SDHC_SEND_RESP_NO_CRC BIT(9)
19 #define MESON_SDHC_SEND_DATA_DIR BIT(10)
20 #define MESON_SDHC_SEND_DATA_STOP BIT(11)
21 #define MESON_SDHC_SEND_R1B BIT(12)
26 #define MESON_SDHC_CTRL_DDR_MODE BIT(2)
27 #define MESON_SDHC_CTRL_TX_CRC_NOCHECK BIT(3)
32 #define MESON_SDHC_CTRL_SDIO_IRQ_MODE BIT(27)
33 #define MESON_SDHC_CTRL_DAT0_IRQ_SEL BIT(28)
37 #define MESON_SDHC_STAT_CMD_BUSY BIT(0)
39 #define MESON_SDHC_STAT_CMD BIT(5)
45 #define MESON_SDHC_CLKC_CLK_DIV GENMASK(11, 0)
46 #define MESON_SDHC_CLKC_CLK_JIC BIT(24)
52 #define MESON_SDHC_PDMA_DMA_MODE BIT(0)
54 #define MESON_SDHC_PDMA_DMA_URGENT BIT(4)
60 #define MESON_SDHC_PDMA_TXFIFO_FILL BIT(31)
67 #define MESON_SDHC_MISC_MANUAL_STOP BIT(28)
73 #define MESON_SDHC_ICTL_RESP_OK BIT(0)
74 #define MESON_SDHC_ICTL_RESP_TIMEOUT BIT(1)
75 #define MESON_SDHC_ICTL_RESP_ERR_CRC BIT(2)
76 #define MESON_SDHC_ICTL_RESP_OK_NOCLEAR BIT(3)
77 #define MESON_SDHC_ICTL_DATA_1PACK_OK BIT(4)
78 #define MESON_SDHC_ICTL_DATA_TIMEOUT BIT(5)
79 #define MESON_SDHC_ICTL_DATA_ERR_CRC BIT(6)
80 #define MESON_SDHC_ICTL_DATA_XFER_OK BIT(7)
81 #define MESON_SDHC_ICTL_RX_HIGHER BIT(8)
82 #define MESON_SDHC_ICTL_RX_LOWER BIT(9)
83 #define MESON_SDHC_ICTL_DAT1_IRQ BIT(10)
84 #define MESON_SDHC_ICTL_DMA_DONE BIT(11)
85 #define MESON_SDHC_ICTL_RXFIFO_FULL BIT(12)
86 #define MESON_SDHC_ICTL_TXFIFO_EMPTY BIT(13)
87 #define MESON_SDHC_ICTL_ADDI_DAT1_IRQ BIT(14)
92 #define MESON_SDHC_ISTA_RESP_OK BIT(0)
93 #define MESON_SDHC_ISTA_RESP_TIMEOUT BIT(1)
94 #define MESON_SDHC_ISTA_RESP_ERR_CRC BIT(2)
95 #define MESON_SDHC_ISTA_RESP_OK_NOCLEAR BIT(3)
96 #define MESON_SDHC_ISTA_DATA_1PACK_OK BIT(4)
97 #define MESON_SDHC_ISTA_DATA_TIMEOUT BIT(5)
98 #define MESON_SDHC_ISTA_DATA_ERR_CRC BIT(6)
99 #define MESON_SDHC_ISTA_DATA_XFER_OK BIT(7)
100 #define MESON_SDHC_ISTA_RX_HIGHER BIT(8)
101 #define MESON_SDHC_ISTA_RX_LOWER BIT(9)
102 #define MESON_SDHC_ISTA_DAT1_IRQ BIT(10)
103 #define MESON_SDHC_ISTA_DMA_DONE BIT(11)
104 #define MESON_SDHC_ISTA_RXFIFO_FULL BIT(12)
105 #define MESON_SDHC_ISTA_TXFIFO_EMPTY BIT(13)
106 #define MESON_SDHC_ISTA_ADDI_DAT1_IRQ BIT(14)
110 #define MESON_SDHC_SRST_MAIN_CTRL BIT(0)
111 #define MESON_SDHC_SRST_RXFIFO BIT(1)
112 #define MESON_SDHC_SRST_TXFIFO BIT(2)
113 #define MESON_SDHC_SRST_DPHY_RX BIT(3)
114 #define MESON_SDHC_SRST_DPHY_TX BIT(4)
115 #define MESON_SDHC_SRST_DMA_IF BIT(5)
118 #define MESON_SDHC_ESTA_11_13 GENMASK(13, 11)
121 #define MESON_SDHC_ENHC_MESON8M2_WRRSP_MODE BIT(0)
122 #define MESON_SDHC_ENHC_MESON8M2_CHK_WRRSP BIT(1)
123 #define MESON_SDHC_ENHC_MESON8M2_CHK_DMA BIT(2)
126 #define MESON_SDHC_ENHC_MESON6_DMA_RD_RESP BIT(16)
127 #define MESON_SDHC_ENHC_MESON6_DMA_WR_RESP BIT(17)
133 #define MESON_SDHC_CLK2_RX_CLK_PHASE GENMASK(11, 0)