Lines Matching +full:11 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Thunderbolt driver - Port/Switch config area registers
65 * struct tb_cap_extended_short - Switch extended short capability
80 * struct tb_cap_extended_long - Switch extended long capability
98 * struct tb_cap_any - Structure capable of hold every capability
130 u32 unknown3:11;
136 bool fl_sk:1; /* send pulse to transfer one bit */
155 u32 __unknown5[7]; /* VSC_CS_5 -> VSC_CS_11 */
156 u32 drom_offset; /* VSC_CS_12: 32 bit register, but eeprom addresses are 16 bit */
195 #define ROUTER_CS_5_SLP BIT(0)
196 #define ROUTER_CS_5_WOP BIT(1)
197 #define ROUTER_CS_5_WOU BIT(2)
198 #define ROUTER_CS_5_WOD BIT(3)
199 #define ROUTER_CS_5_C3S BIT(23)
200 #define ROUTER_CS_5_PTO BIT(24)
201 #define ROUTER_CS_5_UTO BIT(25)
202 #define ROUTER_CS_5_HCO BIT(26)
203 #define ROUTER_CS_5_CV BIT(31)
205 #define ROUTER_CS_6_SLPR BIT(0)
206 #define ROUTER_CS_6_TNS BIT(1)
207 #define ROUTER_CS_6_WOPS BIT(2)
208 #define ROUTER_CS_6_WOUS BIT(3)
209 #define ROUTER_CS_6_HCI BIT(18)
210 #define ROUTER_CS_6_CR BIT(25)
218 #define ROUTER_CS_26_ONS BIT(30)
219 #define ROUTER_CS_26_OV BIT(31)
238 #define TMU_RTR_CS_0_TD BIT(27)
239 #define TMU_RTR_CS_0_UCAP BIT(30)
250 #define TMU_RTR_CS_15_DELAY_AVG_MASK GENMASK(11, 6)
278 u32 max_counters:11;
292 u32 max_in_hop_id:11;
293 u32 max_out_hop_id:11;
307 #define ADP_CS_4_LCK BIT(31)
311 #define ADP_CS_5_DHP BIT(31)
315 #define TMU_ADP_CS_3_UDM BIT(29)
317 #define TMU_ADP_CS_6_DTS BIT(1)
326 #define LANE_ADP_CS_0_CL0S_SUPPORT BIT(26)
327 #define LANE_ADP_CS_0_CL1_SUPPORT BIT(27)
328 #define LANE_ADP_CS_0_CL2_SUPPORT BIT(28)
336 #define LANE_ADP_CS_1_CL0S_ENABLE BIT(10)
337 #define LANE_ADP_CS_1_CL1_ENABLE BIT(11)
338 #define LANE_ADP_CS_1_CL2_ENABLE BIT(12)
339 #define LANE_ADP_CS_1_LD BIT(14)
340 #define LANE_ADP_CS_1_LB BIT(15)
347 #define LANE_ADP_CS_1_PMS BIT(30)
355 #define PORT_CS_1_WNR_WRITE BIT(24)
356 #define PORT_CS_1_NR BIT(25)
357 #define PORT_CS_1_RC BIT(26)
358 #define PORT_CS_1_PND BIT(31)
361 #define PORT_CS_18_BE BIT(8)
362 #define PORT_CS_18_TCM BIT(9)
363 #define PORT_CS_18_CPS BIT(10)
364 #define PORT_CS_18_WOU4S BIT(18)
366 #define PORT_CS_19_PC BIT(3)
367 #define PORT_CS_19_PID BIT(4)
368 #define PORT_CS_19_WOC BIT(16)
369 #define PORT_CS_19_WOD BIT(17)
370 #define PORT_CS_19_WOU4 BIT(18)
376 #define ADP_DP_CS_0_AE BIT(30)
377 #define ADP_DP_CS_0_VE BIT(31)
379 #define ADP_DP_CS_1_AUX_RX_HOPID_MASK GENMASK(21, 11)
380 #define ADP_DP_CS_1_AUX_RX_HOPID_SHIFT 11
382 #define ADP_DP_CS_2_HDP BIT(6)
384 #define ADP_DP_CS_3_HDPC BIT(9)
388 #define DP_STATUS_CTRL_CMHS BIT(25)
389 #define DP_STATUS_CTRL_UF BIT(26)
395 #define DP_COMMON_CAP_RATE_MASK GENMASK(11, 8)
406 #define DP_COMMON_CAP_LTTPR_NS BIT(27)
407 #define DP_COMMON_CAP_DPRX_DONE BIT(31)
411 #define ADP_PCIE_CS_0_PE BIT(31)
415 #define ADP_USB3_CS_0_V BIT(30)
416 #define ADP_USB3_CS_0_PE BIT(31)
418 #define ADP_USB3_CS_1_CUBW_MASK GENMASK(11, 0)
421 #define ADP_USB3_CS_1_HCA BIT(31)
423 #define ADP_USB3_CS_2_AUBW_MASK GENMASK(11, 0)
426 #define ADP_USB3_CS_2_CMR BIT(31)
432 #define ADP_USB3_CS_4_ULV BIT(7)
440 u32 next_hop:11; /*
454 u32 counter:11; /* index into TB_CFG_COUNTERS on this port */
468 #define TB_TIME_VSEC_3_CS_26_TD BIT(22)
476 #define TMU_ADP_CS_6_DISABLE_TMU_OBJ_CL1 BIT(2)
477 #define TMU_ADP_CS_6_DISABLE_TMU_OBJ_CL2 BIT(3)
480 #define TB_PLUG_EVENTS_USB_DISABLE BIT(2)
481 #define TB_PLUG_EVENTS_CS_1_LANE_DISABLE BIT(3)
482 #define TB_PLUG_EVENTS_CS_1_DPOUT_DISABLE BIT(4)
483 #define TB_PLUG_EVENTS_CS_1_LOW_DPIN_DISABLE BIT(5)
484 #define TB_PLUG_EVENTS_CS_1_HIGH_DPIN_DISABLE BIT(6)
491 #define TB_PLUG_EVENTS_PCIE_CMD_RD_WR_MASK BIT(21)
496 #define TB_PLUG_EVENTS_PCIE_CMD_REQ_ACK_MASK BIT(30)
497 #define TB_PLUG_EVENTS_PCIE_CMD_TIMEOUT_MASK BIT(31)
526 #define TB_LC_CS_42_USB_PLUGGED BIT(31)
529 #define TB_LC_PORT_ATTR_BE BIT(12)
532 #define TB_LC_SX_CTRL_WOC BIT(1)
533 #define TB_LC_SX_CTRL_WOD BIT(2)
534 #define TB_LC_SX_CTRL_WODPC BIT(3)
535 #define TB_LC_SX_CTRL_WODPD BIT(4)
536 #define TB_LC_SX_CTRL_WOU4 BIT(5)
537 #define TB_LC_SX_CTRL_WOP BIT(6)
538 #define TB_LC_SX_CTRL_L1C BIT(16)
539 #define TB_LC_SX_CTRL_L1D BIT(17)
540 #define TB_LC_SX_CTRL_L2C BIT(20)
541 #define TB_LC_SX_CTRL_L2D BIT(21)
542 #define TB_LC_SX_CTRL_SLI BIT(29)
543 #define TB_LC_SX_CTRL_UPSTREAM BIT(30)
544 #define TB_LC_SX_CTRL_SLP BIT(31)
546 #define TB_LC_LINK_ATTR_CPS BIT(18)
549 #define TB_LC_LINK_REQ_XHCI_CONNECT BIT(31)