Lines Matching +full:11 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0-only */
17 * the ability to move more than 2^11 counts of data and some extra
38 #define PL080_CONFIG_M2_BE BIT(2)
39 #define PL080_CONFIG_M1_BE BIT(1)
40 #define PL080_CONFIG_ENABLE BIT(0)
72 #define PL080_LLI_LM_AHB2 BIT(0)
74 #define PL080_CONTROL_TC_IRQ_EN BIT(31)
77 #define PL080_CONTROL_PROT_CACHE BIT(30)
78 #define PL080_CONTROL_PROT_BUFF BIT(29)
79 #define PL080_CONTROL_PROT_SYS BIT(28)
80 #define PL080_CONTROL_DST_INCR BIT(27)
81 #define PL080_CONTROL_SRC_INCR BIT(26)
82 #define PL080_CONTROL_DST_AHB2 BIT(25)
83 #define PL080_CONTROL_SRC_AHB2 BIT(24)
92 #define PL080_CONTROL_TRANSFER_SIZE_MASK GENMASK(11, 0)
109 #define PL080N_CONFIG_ITPROT BIT(20)
110 #define PL080N_CONFIG_SECPROT BIT(19)
111 #define PL080_CONFIG_HALT BIT(18)
112 #define PL080_CONFIG_ACTIVE BIT(17) /* RO */
113 #define PL080_CONFIG_LOCK BIT(16)
114 #define PL080_CONFIG_TC_IRQ_MASK BIT(15)
115 #define PL080_CONFIG_ERR_IRQ_MASK BIT(14)
116 #define PL080_CONFIG_FLOW_CONTROL_MASK GENMASK(13, 11)
117 #define PL080_CONFIG_FLOW_CONTROL_SHIFT (11)
122 #define PL080_CONFIG_ENABLE BIT(0)
133 #define FTDMAC020_CH_CSR_TC_MSK BIT(31)
138 #define FTDMAC020_CH_CSR_PROT3 BIT(21)
139 #define FTDMAC020_CH_CSR_PROT2 BIT(20)
140 #define FTDMAC020_CH_CSR_PROT1 BIT(19)
143 #define FTDMAC020_CH_CSR_ABT BIT(15)
144 #define FTDMAC020_CH_CSR_SRC_WIDTH_MSK GENMASK(13, 11)
145 #define FTDMAC020_CH_CSR_SRC_WIDTH_SHIFT (11)
148 #define FTDMAC020_CH_CSR_MODE BIT(7)
154 #define FTDMAC020_CH_CSR_SRC_SEL BIT(2)
155 #define FTDMAC020_CH_CSR_DST_SEL BIT(1)
156 #define FTDMAC020_CH_CSR_EN BIT(0)
164 /* The FTDMAC020 supports 64bit wide transfers */
173 #define FTDMAC020_CH_CFG_BUSY BIT(8)
174 #define FTDMAC020_CH_CFG_INT_ABT_MASK BIT(2)
175 #define FTDMAC020_CH_CFG_INT_ERR_MASK BIT(1)
176 #define FTDMAC020_CH_CFG_INT_TC_MASK BIT(0)
179 #define FTDMAC020_LLI_TC_MSK BIT(28)
188 #define FTDMAC020_LLI_SRC_SEL BIT(17)
189 #define FTDMAC020_LLI_DST_SEL BIT(16)
190 #define FTDMAC020_LLI_TRANSFER_SIZE_MASK GENMASK(11, 0)
195 #define FTDMAC020_CFG_BUSY BIT(8)
196 #define FTDMAC020_CFG_INT_ABT_MSK BIT(2)
197 #define FTDMAC020_CFG_INT_ERR_MSK BIT(1)
198 #define FTDMAC020_CFG_INT_TC_MSK BIT(0)