| /Linux-v6.6/arch/arm64/include/asm/ |
| D | sysreg.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include <linux/kasan-tags.h>
16 #include <asm/gpr-num.h>
22 * [20-19] : Op0
23 * [18-16] : Op1
24 * [15-12] : CRn
25 * [11-8] : CRm
26 * [7-5] : Op2
83 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
96 #define PSTATE_UAO pstate_field(0, 3)
[all …]
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| /Linux-v6.6/arch/powerpc/lib/ |
| D | feature-fixups-test.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 #include <asm/feature-fixups.h>
9 #include <asm/asm-compat.h>
10 #include <asm/ppc-opcode.h>
19 or 1,1,1
21 or 3,3,3
26 or 1,1,1
28 or 3,3,3
31 or 1,1,1
33 or 3,3,3
[all …]
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| /Linux-v6.6/drivers/phy/rockchip/ |
| D | phy-rockchip-inno-hdmi.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 * Author: Zheng Yang <zhengyang@rock-chips.com>
10 #include <linux/clk-provider.h>
16 #include <linux/nvmem-consumer.h>
29 #define RK3228_BYPASS_PWRON_EN BIT(1)
44 #define RK3228_RXSENSE_CLK_CH_ENABLE BIT(3)
46 #define RK3228_RXSENSE_DATA_CH1_ENABLE BIT(1)
50 #define RK3228_TMDS_DRIVER_ENABLE GENMASK(3, 0)
74 #define RK3228_PRE_PLL_TMDSCLK_DIV_A_MASK GENMASK(3, 2)
75 #define RK3228_PRE_PLL_TMDSCLK_DIV_A(x) UPDATE(x, 3, 2)
[all …]
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| /Linux-v6.6/arch/arm64/boot/dts/rockchip/ |
| D | rk3568-pinctrl.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include "rockchip-pinconf.dtsi"
15 /omit-if-no-ref/
16 acodec_pins: acodec-pins {
19 <1 RK_PB1 5 &pcfg_pull_none>,
21 <1 RK_PA1 5 &pcfg_pull_none>,
23 <1 RK_PA0 5 &pcfg_pull_none>,
25 <1 RK_PA7 5 &pcfg_pull_none>,
27 <1 RK_PB0 5 &pcfg_pull_none>,
[all …]
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| /Linux-v6.6/tools/testing/selftests/cgroup/ |
| D | test_cpuset_prs.sh | 2 # SPDX-License-Identifier: GPL-2.0
11 echo "$1"
16 [[ $(id -u) -eq 0 ]] || skip_test "Test must be run as root!"
23 CGROUP2=$(mount -t cgroup2 | head -1 | awk -e '{print $3}')
24 [[ -n "$CGROUP2" ]] || skip_test "Cgroup v2 mount point not found!"
26 CPUS=$(lscpu | grep "^CPU(s):" | sed -e "s/.*:[[:space:]]*//")
27 [[ $CPUS -lt 8 ]] && skip_test "Test needs at least 8 cpus available!"
30 PROG=$1
32 DELAY_FACTOR=1
34 while [[ "$1" = -* ]]
[all …]
|
| /Linux-v6.6/arch/powerpc/boot/ |
| D | string.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
13 addi r5,r3,-1
14 addi r4,r4,-1
15 1: lbzu r0,1(r4)
17 stbu r0,1(r5)
18 bne 1b
26 addi r6,r3,-1
27 addi r4,r4,-1
28 1: lbzu r0,1(r4)
30 stbu r0,1(r6)
[all …]
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| /Linux-v6.6/arch/xtensa/variants/csp/include/variant/ |
| D | tie.h | 2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2015 Cadence Design Systems Inc.
35 #define XCHAL_CP_NUM 1 /* number of coprocessors */
36 #define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */
44 #define XCHAL_CP7_SA_ALIGN 1 /* min alignment of save area */
49 #define XCHAL_CP0_SA_ALIGN 1
51 #define XCHAL_CP1_SA_ALIGN 1
53 #define XCHAL_CP2_SA_ALIGN 1
55 #define XCHAL_CP3_SA_ALIGN 1
57 #define XCHAL_CP4_SA_ALIGN 1
[all …]
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| /Linux-v6.6/fs/exfat/ |
| D | balloc.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2012-2013 Samsung Electronics Co., Ltd.
14 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, 4, 0, 1, 0, 2,/* 0 ~ 19*/
15 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, 5, 0, 1, 0, 2, 0, 1, 0, 3,/* 20 ~ 39*/
16 0, 1, 0, 2, 0, 1, 0, 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2,/* 40 ~ 59*/
17 0, 1, 0, 6, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, 4,/* 60 ~ 79*/
18 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, 5, 0, 1, 0, 2,/* 80 ~ 99*/
19 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, 4, 0, 1, 0, 2, 0, 1, 0, 3,/*100 ~ 119*/
20 0, 1, 0, 2, 0, 1, 0, 7, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2,/*120 ~ 139*/
21 0, 1, 0, 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, 5,/*140 ~ 159*/
[all …]
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| /Linux-v6.6/arch/xtensa/variants/test_kc705_be/include/variant/ |
| D | tie.h | 2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2015 Cadence Design Systems Inc.
36 #define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */
45 #define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */
49 #define XCHAL_CP7_SA_ALIGN 1 /* min alignment of save area */
54 #define XCHAL_CP0_SA_ALIGN 1
56 #define XCHAL_CP2_SA_ALIGN 1
58 #define XCHAL_CP3_SA_ALIGN 1
60 #define XCHAL_CP4_SA_ALIGN 1
62 #define XCHAL_CP5_SA_ALIGN 1
[all …]
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| /Linux-v6.6/tools/arch/arm64/include/asm/ |
| D | sysreg.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
19 * [20-19] : Op0
20 * [18-16] : Op1
21 * [15-12] : CRn
22 * [11-8] : CRm
23 * [7-5] : Op2
80 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
92 #define PSTATE_UAO pstate_field(0, 3)
93 #define PSTATE_SSBS pstate_field(3, 1)
94 #define PSTATE_TCO pstate_field(3, 4)
[all …]
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| /Linux-v6.6/Documentation/input/devices/ |
| D | elantech.rst | 4 Copyright (C) 2007-2008 Arjan Opmeer <arjan@opmeer.net>
6 Extra information for hardware version 1 found and
15 1. Introduction
17 3. Differentiating hardware versions
18 4. Hardware version 1
25 5.2.1 Parity checking and packet re-synchronization
27 5.2.3 Two finger touch
28 6. Hardware version 3
31 6.2.1 One/Three finger touch
36 7.2.1 Status packet
[all …]
|
| /Linux-v6.6/include/dt-bindings/pinctrl/ |
| D | pads-imx8qm.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
12 #define IMX8QM_SIM0_RST 1
14 #define IMX8QM_SIM0_PD 3
285 #define IMX8QM_SIM0_CLK_LSIO_GPIO0_IO00 IMX8QM_SIM0_CLK 3
287 #define IMX8QM_SIM0_RST_LSIO_GPIO0_IO01 IMX8QM_SIM0_RST 3
289 #define IMX8QM_SIM0_IO_LSIO_GPIO0_IO02 IMX8QM_SIM0_IO 3
291 #define IMX8QM_SIM0_PD_DMA_I2C3_SCL IMX8QM_SIM0_PD 1
292 #define IMX8QM_SIM0_PD_LSIO_GPIO0_IO03 IMX8QM_SIM0_PD 3
294 #define IMX8QM_SIM0_POWER_EN_DMA_I2C3_SDA IMX8QM_SIM0_POWER_EN 1
295 #define IMX8QM_SIM0_POWER_EN_LSIO_GPIO0_IO04 IMX8QM_SIM0_POWER_EN 3
[all …]
|
| /Linux-v6.6/arch/arm/mach-omap1/ |
| D | mux.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * linux/arch/arm/mach-omap1/mux.c
7 * Copyright (C) 2003 - 2008 Nokia Corporation
15 #include <linux/soc/ti/omap1-io.h>
30 MUX_CFG("UART1_TX", 9, 21, 1, 2, 3, 0, NA, 0, 0)
31 MUX_CFG("UART1_RTS", 9, 12, 1, 2, 0, 0, NA, 0, 0)
34 MUX_CFG("UART2_TX", C, 27, 1, 3, 3, 0, NA, 0, 0)
35 MUX_CFG("UART2_RX", C, 18, 0, 3, 1, 1, NA, 0, 0)
36 MUX_CFG("UART2_CTS", C, 21, 0, 3, 1, 1, NA, 0, 0)
37 MUX_CFG("UART2_RTS", C, 24, 1, 3, 2, 0, NA, 0, 0)
[all …]
|
| /Linux-v6.6/drivers/mtd/nand/raw/ |
| D | nand_ids.c | 1 // SPDX-License-Identifier: GPL-2.0-only
29 {"TC58NVG0S3E 1G 3.3V 8-bit",
31 SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), },
32 {"TC58NVG2S0F 4G 3.3V 8-bit",
35 {"TC58NVG2S0H 4G 3.3V 8-bit",
38 {"TC58NVG3S0F 8G 3.3V 8-bit",
41 {"TC58NVG5D2 32G 3.3V 8-bit",
44 {"TC58NVG6D2 64G 3.3V 8-bit",
47 {"SDTNQGAMA 64G 3.3V 8-bit",
50 {"SDTNRGAMA 64G 3.3V 8-bit",
[all …]
|
| /Linux-v6.6/arch/xtensa/variants/test_kc705_hifi/include/variant/ |
| D | tie.h | 2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2014 Tensilica Inc.
36 #define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */
45 #define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */
49 #define XCHAL_CP7_SA_ALIGN 1 /* min alignment of save area */
54 #define XCHAL_CP0_SA_ALIGN 1
56 #define XCHAL_CP2_SA_ALIGN 1
58 #define XCHAL_CP3_SA_ALIGN 1
60 #define XCHAL_CP4_SA_ALIGN 1
62 #define XCHAL_CP5_SA_ALIGN 1
[all …]
|
| /Linux-v6.6/tools/testing/selftests/kvm/aarch64/ |
| D | get-reg-list.c | 1 // SPDX-License-Identifier: GPL-2.0
27 ARM64_SYS_REG(3, 0, 2, 0, 3), /* TCR2_EL1 */
28 ARM64_SYS_REG(3, 0, 0, 7, 3), /* ID_AA64MMFR3_EL1 */
30 1
33 ARM64_SYS_REG(3, 0, 10, 2, 2), /* PIRE0_EL1 */
34 ARM64_SYS_REG(3, 0, 0, 7, 3), /* ID_AA64MMFR3_EL1 */
36 1
39 ARM64_SYS_REG(3, 0, 10, 2, 3), /* PIR_EL1 */
40 ARM64_SYS_REG(3, 0, 0, 7, 3), /* ID_AA64MMFR3_EL1 */
42 1
[all …]
|
| /Linux-v6.6/Documentation/userspace-api/media/v4l/ |
| D | pixfmt-rgb.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _pixfmt-rgb:
22 (including capture queues of mem-to-mem devices) fill the alpha component in
25 but can set the alpha bit to a user-configurable value, the
26 :ref:`V4L2_CID_ALPHA_COMPONENT <v4l2-alpha-component>` control is used to
31 :ref:`Output <output>` devices (including output queues of mem-to-mem devices
44 - In all the tables that follow, bit 7 is the most significant bit in a byte.
45 - 'r', 'g' and 'b' denote bits of the red, green and blue components
54 based on the order of the RGB components as seen in a 8-, 16- or 32-bit word,
57 for each component. For instance, the RGB565 format stores a pixel in a 16-bit
[all …]
|
| /Linux-v6.6/drivers/pinctrl/pxa/ |
| D | pinctrl-pxa27x.c | 1 // SPDX-License-Identifier: GPL-2.0-only
12 #include "pinctrl-pxa2xx.h"
16 PXA_GPIO_ONLY_PIN(PXA_PINCTRL_PIN(1)),
18 PXA_FUNCTION(0, 3, "FFCTS"),
19 PXA_FUNCTION(1, 1, "HZ_CLK"),
20 PXA_FUNCTION(1, 3, "CHOUT<0>")),
22 PXA_FUNCTION(0, 1, "FFDCD"),
23 PXA_FUNCTION(0, 3, "USB_P3_5"),
24 PXA_FUNCTION(1, 1, "HZ_CLK"),
25 PXA_FUNCTION(1, 3, "CHOUT<1>")),
[all …]
|
| /Linux-v6.6/tools/testing/selftests/drivers/net/mlxsw/spectrum/ |
| D | vxlan_flooding_ipv6.sh | 2 # SPDX-License-Identifier: GPL-2.0
9 # +-----------------------+
12 # | | 2001:db8:1::1/64 |
13 # +----|------------------+
15 # +----|----------------------------------------------------------------------+
17 # | +--|--------------------------------------------------------------------+ |
21 # | | local 2001:db8:2::1 | |
24 # | +-----------------------------------------------------------------------+ |
26 # | 2001:db8:2::0/64 via 2001:db8:3::2 |
29 # | | 2001:db8:3::1/64 |
[all …]
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| /Linux-v6.6/tools/testing/selftests/drivers/net/mlxsw/ |
| D | fib_offload.sh | 2 # SPDX-License-Identifier: GPL-2.0
20 simple_if_init $tor1_p1 2001:db8:1::2/128 2001:db8:1::3/128
25 simple_if_fini $tor1_p1 2001:db8:1::2/128 2001:db8:1::3/128
30 simple_if_init $tor2_p1 2001:db8:2::2/128 2001:db8:2::3/128
35 simple_if_fini $tor2_p1 2001:db8:2::2/128 2001:db8:2::3/128
43 __addr_add_del $spine_p1 add 2001:db8:1::1/64
44 __addr_add_del $spine_p2 add 2001:db8:2::1/64
49 __addr_add_del $spine_p2 del 2001:db8:2::1/64
50 __addr_add_del $spine_p1 del 2001:db8:1::1/64
58 local pfx="$1"; shift
[all …]
|
| /Linux-v6.6/Documentation/driver-api/media/drivers/ccs/ |
| D | ccs-regs.asc | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
2 # Copyright (C) 2019--2020 Intel Corporation
5 # - f field LSB MSB rflags
6 # - e enum value # after a field
7 # - e enum value [LSB MSB]
8 # - b bool bit
9 # - l arg name min max elsize [discontig...]
13 # v1.1 defined in version 1.1
23 - e GRBG 0
24 - e RGGB 1
[all …]
|
| /Linux-v6.6/tools/perf/util/ |
| D | expr.y | 3 #define YYDEBUG 1
8 #define IN_EXPR_Y 1
10 #include "expr-bison.h"
16 %parse-param { double *final_val }
17 %parse-param { struct expr_parse_ctx *ctx }
18 %parse-param { bool compute_ids }
19 %parse-param {void *scanner}
20 %lex-param {void* scanner}
48 %left '-' '+'
73 /* During computing ids, does val represent a constant (non-BOTTOM) value? */
[all …]
|
| /Linux-v6.6/sound/soc/codecs/ |
| D | max98926.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * max98926.h -- MAX98926 ALSA SoC Audio driver
4 * Copyright 2013-2015 Maxim Integrated Products
73 #define MAX98926_REG_CNT (MAX98926_R03A_BOOST_LIMITER+1)
75 #define MAX98926_PDM_CURRENT_MASK (1<<7)
77 #define MAX98926_PDM_VOLTAGE_MASK (1<<3)
78 #define MAX98926_PDM_VOLTAGE_SHIFT 3
79 #define MAX98926_PDM_CHANNEL_0_MASK (1<<2)
81 #define MAX98926_PDM_CHANNEL_1_MASK (1<<6)
84 #define MAX98926_PDM_CHANNEL_0_HIZ 1
[all …]
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| D | max98925.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * max98925.h -- MAX98925 ALSA SoC Audio driver
5 * Copyright 2013-2015 Maxim Integrated Products
73 #define MAX98925_REG_CNT (MAX98925_R03A_BOOST_LIMITER+1)
78 #define M98925_THERMWARN_STATUS_MASK (1<<3)
79 #define M98925_THERMWARN_STATUS_SHIFT 3
80 #define M98925_THERMWARN_STATUS_WIDTH 1
81 #define M98925_THERMSHDN_STATUS_MASK (1<<1)
82 #define M98925_THERMSHDN_STATUS_SHIFT 1
83 #define M98925_THERMSHDN_STATUS_WIDTH 1
[all …]
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| D | sma1303.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * sma1303.h -- sma1303 ALSA SoC Audio driver
27 #define SMA1303_I2C_RETRY_COUNT 3
109 #define SMA1303_RESETBYI2C_MASK (1<<1)
110 #define SMA1303_RESETBYI2C_NORMAL (0<<1)
111 #define SMA1303_RESETBYI2C_RESET (1<<1)
113 #define SMA1303_POWER_MASK (1<<0)
115 #define SMA1303_POWER_ON (1<<0)
118 #define SMA1303_CONTROLLER_DEVICE_MASK (1<<7)
120 #define SMA1303_CONTROLLER_MODE (1<<7)
[all …]
|
