Lines Matching +full:1 +full:- +full:3
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * max98925.h -- MAX98925 ALSA SoC Audio driver
5 * Copyright 2013-2015 Maxim Integrated Products
73 #define MAX98925_REG_CNT (MAX98925_R03A_BOOST_LIMITER+1)
78 #define M98925_THERMWARN_STATUS_MASK (1<<3)
79 #define M98925_THERMWARN_STATUS_SHIFT 3
80 #define M98925_THERMWARN_STATUS_WIDTH 1
81 #define M98925_THERMSHDN_STATUS_MASK (1<<1)
82 #define M98925_THERMSHDN_STATUS_SHIFT 1
83 #define M98925_THERMSHDN_STATUS_WIDTH 1
86 #define M98925_SPKCURNT_STATUS_MASK (1<<5)
88 #define M98925_SPKCURNT_STATUS_WIDTH 1
89 #define M98925_WATCHFAIL_STATUS_MASK (1<<4)
91 #define M98925_WATCHFAIL_STATUS_WIDTH 1
92 #define M98925_ALCINFH_STATUS_MASK (1<<3)
93 #define M98925_ALCINFH_STATUS_SHIFT 3
94 #define M98925_ALCINFH_STATUS_WIDTH 1
95 #define M98925_ALCACT_STATUS_MASK (1<<2)
97 #define M98925_ALCACT_STATUS_WIDTH 1
98 #define M98925_ALCMUT_STATUS_MASK (1<<1)
99 #define M98925_ALCMUT_STATUS_SHIFT 1
100 #define M98925_ALCMUT_STATUS_WIDTH 1
101 #define M98925_ACLP_STATUS_MASK (1<<0)
103 #define M98925_ACLP_STATUS_WIDTH 1
106 #define M98925_SLOTOVRN_STATUS_MASK (1<<6)
108 #define M98925_SLOTOVRN_STATUS_WIDTH 1
109 #define M98925_INVALSLOT_STATUS_MASK (1<<5)
111 #define M98925_INVALSLOT_STATUS_WIDTH 1
112 #define M98925_SLOTCNFLT_STATUS_MASK (1<<4)
114 #define M98925_SLOTCNFLT_STATUS_WIDTH 1
115 #define M98925_VBSTOVFL_STATUS_MASK (1<<3)
116 #define M98925_VBSTOVFL_STATUS_SHIFT 3
117 #define M98925_VBSTOVFL_STATUS_WIDTH 1
118 #define M98925_VBATOVFL_STATUS_MASK (1<<2)
120 #define M98925_VBATOVFL_STATUS_WIDTH 1
121 #define M98925_IMONOVFL_STATUS_MASK (1<<1)
122 #define M98925_IMONOVFL_STATUS_SHIFT 1
123 #define M98925_IMONOVFL_STATUS_WIDTH 1
124 #define M98925_VMONOVFL_STATUS_MASK (1<<0)
126 #define M98925_VMONOVFL_STATUS_WIDTH 1
129 #define M98925_THERMWARN_END_STATE_MASK (1<<3)
130 #define M98925_THERMWARN_END_STATE_SHIFT 3
131 #define M98925_THERMWARN_END_STATE_WIDTH 1
132 #define M98925_THERMWARN_BGN_STATE_MASK (1<<2)
133 #define M98925_THERMWARN_BGN_STATE_SHIFT 1
134 #define M98925_THERMWARN_BGN_STATE_WIDTH 1
135 #define M98925_THERMSHDN_END_STATE_MASK (1<<1)
136 #define M98925_THERMSHDN_END_STATE_SHIFT 1
137 #define M98925_THERMSHDN_END_STATE_WIDTH 1
138 #define M98925_THERMSHDN_BGN_STATE_MASK (1<<0)
140 #define M98925_THERMSHDN_BGN_STATE_WIDTH 1
143 #define M98925_SPRCURNT_STATE_MASK (1<<5)
145 #define M98925_SPRCURNT_STATE_WIDTH 1
146 #define M98925_WATCHFAIL_STATE_MASK (1<<4)
148 #define M98925_WATCHFAIL_STATE_WIDTH 1
149 #define M98925_ALCINFH_STATE_MASK (1<<3)
150 #define M98925_ALCINFH_STATE_SHIFT 3
151 #define M98925_ALCINFH_STATE_WIDTH 1
152 #define M98925_ALCACT_STATE_MASK (1<<2)
154 #define M98925_ALCACT_STATE_WIDTH 1
155 #define M98925_ALCMUT_STATE_MASK (1<<1)
156 #define M98925_ALCMUT_STATE_SHIFT 1
157 #define M98925_ALCMUT_STATE_WIDTH 1
158 #define M98925_ALCP_STATE_MASK (1<<0)
160 #define M98925_ALCP_STATE_WIDTH 1
163 #define M98925_SLOTOVRN_STATE_MASK (1<<6)
165 #define M98925_SLOTOVRN_STATE_WIDTH 1
166 #define M98925_INVALSLOT_STATE_MASK (1<<5)
168 #define M98925_INVALSLOT_STATE_WIDTH 1
169 #define M98925_SLOTCNFLT_STATE_MASK (1<<4)
171 #define M98925_SLOTCNFLT_STATE_WIDTH 1
172 #define M98925_VBSTOVFL_STATE_MASK (1<<3)
173 #define M98925_VBSTOVFL_STATE_SHIFT 3
174 #define M98925_VBSTOVFL_STATE_WIDTH 1
175 #define M98925_VBATOVFL_STATE_MASK (1<<2)
177 #define M98925_VBATOVFL_STATE_WIDTH 1
178 #define M98925_IMONOVFL_STATE_MASK (1<<1)
179 #define M98925_IMONOVFL_STATE_SHIFT 1
180 #define M98925_IMONOVFL_STATE_WIDTH 1
181 #define M98925_VMONOVFL_STATE_MASK (1<<0)
183 #define M98925_VMONOVFL_STATE_WIDTH 1
186 #define M98925_THERMWARN_END_FLAG_MASK (1<<3)
187 #define M98925_THERMWARN_END_FLAG_SHIFT 3
188 #define M98925_THERMWARN_END_FLAG_WIDTH 1
189 #define M98925_THERMWARN_BGN_FLAG_MASK (1<<2)
191 #define M98925_THERMWARN_BGN_FLAG_WIDTH 1
192 #define M98925_THERMSHDN_END_FLAG_MASK (1<<1)
193 #define M98925_THERMSHDN_END_FLAG_SHIFT 1
194 #define M98925_THERMSHDN_END_FLAG_WIDTH 1
195 #define M98925_THERMSHDN_BGN_FLAG_MASK (1<<0)
197 #define M98925_THERMSHDN_BGN_FLAG_WIDTH 1
200 #define M98925_SPKCURNT_FLAG_MASK (1<<5)
202 #define M98925_SPKCURNT_FLAG_WIDTH 1
203 #define M98925_WATCHFAIL_FLAG_MASK (1<<4)
205 #define M98925_WATCHFAIL_FLAG_WIDTH 1
206 #define M98925_ALCINFH_FLAG_MASK (1<<3)
207 #define M98925_ALCINFH_FLAG_SHIFT 3
208 #define M98925_ALCINFH_FLAG_WIDTH 1
209 #define M98925_ALCACT_FLAG_MASK (1<<2)
211 #define M98925_ALCACT_FLAG_WIDTH 1
212 #define M98925_ALCMUT_FLAG_MASK (1<<1)
213 #define M98925_ALCMUT_FLAG_SHIFT 1
214 #define M98925_ALCMUT_FLAG_WIDTH 1
215 #define M98925_ALCP_FLAG_MASK (1<<0)
217 #define M98925_ALCP_FLAG_WIDTH 1
220 #define M98925_SLOTOVRN_FLAG_MASK (1<<6)
222 #define M98925_SLOTOVRN_FLAG_WIDTH 1
223 #define M98925_INVALSLOT_FLAG_MASK (1<<5)
225 #define M98925_INVALSLOT_FLAG_WIDTH 1
226 #define M98925_SLOTCNFLT_FLAG_MASK (1<<4)
228 #define M98925_SLOTCNFLT_FLAG_WIDTH 1
229 #define M98925_VBSTOVFL_FLAG_MASK (1<<3)
230 #define M98925_VBSTOVFL_FLAG_SHIFT 3
231 #define M98925_VBSTOVFL_FLAG_WIDTH 1
232 #define M98925_VBATOVFL_FLAG_MASK (1<<2)
234 #define M98925_VBATOVFL_FLAG_WIDTH 1
235 #define M98925_IMONOVFL_FLAG_MASK (1<<1)
236 #define M98925_IMONOVFL_FLAG_SHIFT 1
237 #define M98925_IMONOVFL_FLAG_WIDTH 1
238 #define M98925_VMONOVFL_FLAG_MASK (1<<0)
240 #define M98925_VMONOVFL_FLAG_WIDTH 1
243 #define M98925_THERMWARN_END_EN_MASK (1<<3)
244 #define M98925_THERMWARN_END_EN_SHIFT 3
245 #define M98925_THERMWARN_END_EN_WIDTH 1
246 #define M98925_THERMWARN_BGN_EN_MASK (1<<2)
248 #define M98925_THERMWARN_BGN_EN_WIDTH 1
249 #define M98925_THERMSHDN_END_EN_MASK (1<<1)
250 #define M98925_THERMSHDN_END_EN_SHIFT 1
251 #define M98925_THERMSHDN_END_EN_WIDTH 1
252 #define M98925_THERMSHDN_BGN_EN_MASK (1<<0)
254 #define M98925_THERMSHDN_BGN_EN_WIDTH 1
257 #define M98925_SPKCURNT_EN_MASK (1<<5)
259 #define M98925_SPKCURNT_EN_WIDTH 1
260 #define M98925_WATCHFAIL_EN_MASK (1<<4)
262 #define M98925_WATCHFAIL_EN_WIDTH 1
263 #define M98925_ALCINFH_EN_MASK (1<<3)
264 #define M98925_ALCINFH_EN_SHIFT 3
265 #define M98925_ALCINFH_EN_WIDTH 1
266 #define M98925_ALCACT_EN_MASK (1<<2)
268 #define M98925_ALCACT_EN_WIDTH 1
269 #define M98925_ALCMUT_EN_MASK (1<<1)
270 #define M98925_ALCMUT_EN_SHIFT 1
271 #define M98925_ALCMUT_EN_WIDTH 1
272 #define M98925_ALCP_EN_MASK (1<<0)
274 #define M98925_ALCP_EN_WIDTH 1
277 #define M98925_SLOTOVRN_EN_MASK (1<<6)
279 #define M98925_SLOTOVRN_EN_WIDTH 1
280 #define M98925_INVALSLOT_EN_MASK (1<<5)
282 #define M98925_INVALSLOT_EN_WIDTH 1
283 #define M98925_SLOTCNFLT_EN_MASK (1<<4)
285 #define M98925_SLOTCNFLT_EN_WIDTH 1
286 #define M98925_VBSTOVFL_EN_MASK (1<<3)
287 #define M98925_VBSTOVFL_EN_SHIFT 3
288 #define M98925_VBSTOVFL_EN_WIDTH 1
289 #define M98925_VBATOVFL_EN_MASK (1<<2)
291 #define M98925_VBATOVFL_EN_WIDTH 1
292 #define M98925_IMONOVFL_EN_MASK (1<<1)
293 #define M98925_IMONOVFL_EN_SHIFT 1
294 #define M98925_IMONOVFL_EN_WIDTH 1
295 #define M98925_VMONOVFL_EN_MASK (1<<0)
297 #define M98925_VMONOVFL_EN_WIDTH 1
300 #define M98925_THERMWARN_END_CLR_MASK (1<<3)
301 #define M98925_THERMWARN_END_CLR_SHIFT 3
302 #define M98925_THERMWARN_END_CLR_WIDTH 1
303 #define M98925_THERMWARN_BGN_CLR_MASK (1<<2)
305 #define M98925_THERMWARN_BGN_CLR_WIDTH 1
306 #define M98925_THERMSHDN_END_CLR_MASK (1<<1)
307 #define M98925_THERMSHDN_END_CLR_SHIFT 1
308 #define M98925_THERMSHDN_END_CLR_WIDTH 1
309 #define M98925_THERMSHDN_BGN_CLR_MASK (1<<0)
311 #define M98925_THERMSHDN_BGN_CLR_WIDTH 1
314 #define M98925_SPKCURNT_CLR_MASK (1<<5)
316 #define M98925_SPKCURNT_CLR_WIDTH 1
317 #define M98925_WATCHFAIL_CLR_MASK (1<<4)
319 #define M98925_WATCHFAIL_CLR_WIDTH 1
320 #define M98925_ALCINFH_CLR_MASK (1<<3)
321 #define M98925_ALCINFH_CLR_SHIFT 3
322 #define M98925_ALCINFH_CLR_WIDTH 1
323 #define M98925_ALCACT_CLR_MASK (1<<2)
325 #define M98925_ALCACT_CLR_WIDTH 1
326 #define M98925_ALCMUT_CLR_MASK (1<<1)
327 #define M98925_ALCMUT_CLR_SHIFT 1
328 #define M98925_ALCMUT_CLR_WIDTH 1
329 #define M98925_ALCP_CLR_MASK (1<<0)
331 #define M98925_ALCP_CLR_WIDTH 1
334 #define M98925_SLOTOVRN_CLR_MASK (1<<6)
336 #define M98925_SLOTOVRN_CLR_WIDTH 1
337 #define M98925_INVALSLOT_CLR_MASK (1<<5)
339 #define M98925_INVALSLOT_CLR_WIDTH 1
340 #define M98925_SLOTCNFLT_CLR_MASK (1<<4)
342 #define M98925_SLOTCNFLT_CLR_WIDTH 1
343 #define M98925_VBSTOVFL_CLR_MASK (1<<3)
344 #define M98925_VBSTOVFL_CLR_SHIFT 3
345 #define M98925_VBSTOVFL_CLR_WIDTH 1
346 #define M98925_VBATOVFL_CLR_MASK (1<<2)
348 #define M98925_VBATOVFL_CLR_WIDTH 1
349 #define M98925_IMONOVFL_CLR_MASK (1<<1)
350 #define M98925_IMONOVFL_CLR_SHIFT 1
351 #define M98925_IMONOVFL_CLR_WIDTH 1
352 #define M98925_VMONOVFL_CLR_MASK (1<<0)
354 #define M98925_VMONOVFL_CLR_WIDTH 1
357 #define M98925_ER_THERMWARN_EN_MASK (1<<7)
359 #define M98925_ER_THERMWARN_EN_WIDTH 1
362 #define M98925_ER_THERMWARN_MAP_WIDTH 3
365 #define M98925_ER_ALCMUT_EN_MASK (1<<7)
367 #define M98925_ER_ALCMUT_EN_WIDTH 1
370 #define M98925_ER_ALCMUT_MAP_WIDTH 3
371 #define M98925_ER_ALCP_EN_MASK (1<<3)
372 #define M98925_ER_ALCP_EN_SHIFT 3
373 #define M98925_ER_ALCP_EN_WIDTH 1
376 #define M98925_ER_ALCP_MAP_WIDTH 3
379 #define M98925_ER_ALCINFH_EN_MASK (1<<7)
381 #define M98925_ER_ALCINFH_EN_WIDTH 1
384 #define M98925_ER_ALCINFH_MAP_WIDTH 3
385 #define M98925_ER_ALCACT_EN_MASK (1<<3)
386 #define M98925_ER_ALCACT_EN_SHIFT 3
387 #define M98925_ER_ALCACT_EN_WIDTH 1
390 #define M98925_ER_ALCACT_MAP_WIDTH 3
393 #define M98925_ER_SPKCURNT_EN_MASK (1<<7)
395 #define M98925_ER_SPKCURNT_EN_WIDTH 1
398 #define M98925_ER_SPKCURNT_MAP_WIDTH 3
404 #define M98925_ER_IMONOVFL_EN_MASK (1<<7)
406 #define M98925_ER_IMONOVFL_EN_WIDTH 1
409 #define M98925_ER_IMONOVFL_MAP_WIDTH 3
410 #define M98925_ER_VMONOVFL_EN_MASK (1<<3)
411 #define M98925_ER_VMONOVFL_EN_SHIFT 3
412 #define M98925_ER_VMONOVFL_EN_WIDTH 1
415 #define M98925_ER_VMONOVFL_MAP_WIDTH 3
418 #define M98925_ER_VBSTOVFL_EN_MASK (1<<7)
420 #define M98925_ER_VBSTOVFL_EN_WIDTH 1
423 #define M98925_ER_VBSTOVFL_MAP_WIDTH 3
424 #define M98925_ER_VBATOVFL_EN_MASK (1<<3)
425 #define M98925_ER_VBATOVFL_EN_SHIFT 3
426 #define M98925_ER_VBATOVFL_EN_WIDTH 1
429 #define M98925_ER_VBATOVFL_MAP_WIDTH 3
432 #define M98925_ER_INVALSLOT_EN_MASK (1<<7)
434 #define M98925_ER_INVALSLOT_EN_WIDTH 1
437 #define M98925_ER_INVALSLOT_MAP_WIDTH 3
438 #define M98925_ER_SLOTCNFLT_EN_MASK (1<<3)
439 #define M98925_ER_SLOTCNFLT_EN_SHIFT 3
440 #define M98925_ER_SLOTCNFLT_EN_WIDTH 1
443 #define M98925_ER_SLOTCNFLT_MAP_WIDTH 3
446 #define M98925_ER_SLOTOVRN_EN_MASK (1<<3)
447 #define M98925_ER_SLOTOVRN_EN_SHIFT 3
448 #define M98925_ER_SLOTOVRN_EN_WIDTH 1
451 #define M98925_ER_SLOTOVRN_MAP_WIDTH 3
454 #define M98925_DAI_CLK_SOURCE_MASK (1<<6)
456 #define M98925_DAI_CLK_SOURCE_WIDTH 1
468 #define M98925_DAI_MAS_MASK (1<<3)
469 #define M98925_DAI_MAS_SHIFT 3
470 #define M98925_DAI_MAS_WIDTH 1
473 #define M98925_DAI_BSEL_WIDTH 3
476 #define M98925_DAI_BSEL_48 (1 << M98925_DAI_BSEL_SHIFT)
504 #define M98925_DAI_EXTBCLK_HIZ_MASK (1<<4)
506 #define M98925_DAI_EXTBCLK_HIZ_WIDTH 1
507 #define M98925_DAI_WCI_MASK (1<<3)
508 #define M98925_DAI_WCI_SHIFT 3
509 #define M98925_DAI_WCI_WIDTH 1
510 #define M98925_DAI_BCI_MASK (1<<2)
512 #define M98925_DAI_BCI_WIDTH 1
513 #define M98925_DAI_DLY_MASK (1<<1)
514 #define M98925_DAI_DLY_SHIFT 1
515 #define M98925_DAI_DLY_WIDTH 1
516 #define M98925_DAI_TDM_MASK (1<<0)
518 #define M98925_DAI_TDM_WIDTH 1
520 #define M98925_DAI_CHANSZ_16 (1 << M98925_DAI_CHANSZ_SHIFT)
522 #define M98925_DAI_CHANSZ_32 (3 << M98925_DAI_CHANSZ_SHIFT)
525 #define M98925_DAI_DO_EN_MASK (1<<7)
527 #define M98925_DAI_DO_EN_WIDTH 1
528 #define M98925_DAI_DIN_EN_MASK (1<<6)
530 #define M98925_DAI_DIN_EN_WIDTH 1
531 #define M98925_DAI_INR_SOURCE_MASK (0x07<<3)
532 #define M98925_DAI_INR_SOURCE_SHIFT 3
533 #define M98925_DAI_INR_SOURCE_WIDTH 3
536 #define M98925_DAI_INL_SOURCE_WIDTH 3
539 #define M98925_DAI_VMON_EN_MASK (1<<5)
541 #define M98925_DAI_VMON_EN_WIDTH 1
547 #define M98925_DAI_VMON_SLOT_01_02 (1 << M98925_DAI_VMON_SLOT_SHIFT)
549 #define M98925_DAI_VMON_SLOT_03_04 (3 << M98925_DAI_VMON_SLOT_SHIFT)
579 #define M98925_DAI_IMON_EN_MASK (1<<5)
581 #define M98925_DAI_IMON_EN_WIDTH 1
587 #define M98925_DAI_IMON_SLOT_01_02 (1 << M98925_DAI_IMON_SLOT_SHIFT)
589 #define M98925_DAI_IMON_SLOT_03_04 (3 << M98925_DAI_IMON_SLOT_SHIFT)
619 #define M98925_DAI_VBAT_EN_MASK (1<<5)
621 #define M98925_DAI_VBAT_EN_WIDTH 1
627 #define M98925_DAI_VBST_EN_MASK (1<<5)
629 #define M98925_DAI_VBST_EN_WIDTH 1
635 #define M98925_DAI_FLAG_EN_MASK (1<<5)
637 #define M98925_DAI_FLAG_EN_WIDTH 1
668 #define M98925_ADC_DITHER_EN_MASK (1<<7)
670 #define M98925_ADC_DITHER_EN_WIDTH 1
671 #define M98925_IV_DCB_EN_MASK (1<<6)
673 #define M98925_IV_DCB_EN_WIDTH 1
674 #define M98925_DAC_DITHER_EN_MASK (1<<4)
676 #define M98925_DAC_DITHER_EN_WIDTH 1
677 #define M98925_DAC_FILTER_MODE_MASK (1<<3)
678 #define M98925_DAC_FILTER_MODE_SHIFT 3
679 #define M98925_DAC_FILTER_MODE_WIDTH 1
682 #define M98925_DAC_HPF_WIDTH 3
684 #define M98925_DAC_HPF_DC_BLOCK (1 << M98925_DAC_HPF_SHIFT)
686 #define M98925_DAC_HPF_EN_200 (3 << M98925_DAC_HPF_SHIFT)
699 #define M98925_DAC_IN_SEL_RIGHT_DAI (1 << M98925_DAC_IN_SEL_SHIFT)
701 #define M98925_DAC_IN_SEL_DIV2_SUMMED_DAI (3 << M98925_DAC_IN_SEL_SHIFT)
704 #define M98925_SPK_RMP_EN_MASK (1<<1)
705 #define M98925_SPK_RMP_EN_SHIFT 1
706 #define M98925_SPK_RMP_EN_WIDTH 1
707 #define M98925_SPK_ZCD_EN_MASK (1<<0)
709 #define M98925_SPK_ZCD_EN_WIDTH 1
712 #define M98925_SPK_MODE_MASK (1<<0)
714 #define M98925_SPK_MODE_WIDTH 1
717 #define M98925_ALC_EN_MASK (1<<5)
719 #define M98925_ALC_EN_WIDTH 1
730 #define M98925_ALC_ATK_RATE_WIDTH 3
738 #define M98925_ALC_RLS_RATE_WIDTH 3
741 #define M98925_ALC_RLS_TGR_MASK (1<<0)
743 #define M98925_ALC_RLS_TGR_WIDTH 1
746 #define M98925_ALC_MUTE_EN_MASK (1<<7)
748 #define M98925_ALC_MUTE_EN_WIDTH 1
751 #define M98925_ALC_MUTE_DLY_WIDTH 3
754 #define M98925_ALC_RLS_DBT_WIDTH 3
757 #define M98925_BST_SYNC_MASK (1<<7)
759 #define M98925_BST_SYNC_WIDTH 1
768 #define M98925_BST_EN_MASK (1<<7)
770 #define M98925_BST_EN_WIDTH 1
771 #define M98925_WATCH_EN_MASK (1<<6)
773 #define M98925_WATCH_EN_WIDTH 1
774 #define M98925_CLKMON_EN_MASK (1<<5)
776 #define M98925_CLKMON_EN_WIDTH 1
777 #define M98925_SPK_EN_MASK (1<<4)
779 #define M98925_SPK_EN_WIDTH 1
780 #define M98925_ADC_VBST_EN_MASK (1<<3)
781 #define M98925_ADC_VBST_EN_SHIFT 3
782 #define M98925_ADC_VBST_EN_WIDTH 1
783 #define M98925_ADC_VBAT_EN_MASK (1<<2)
785 #define M98925_ADC_VBAT_EN_WIDTH 1
786 #define M98925_ADC_IMON_EN_MASK (1<<1)
787 #define M98925_ADC_IMON_EN_SHIFT 1
788 #define M98925_ADC_IMON_EN_WIDTH 1
789 #define M98925_ADC_VMON_EN_MASK (1<<0)
791 #define M98925_ADC_VMON_EN_WIDTH 1
805 #define M98925_EN_MASK (1<<7)
807 #define M98925_EN_WIDTH 1
810 #define M98925_BST_ILIM_MASK (0x1F<<3)
811 #define M98925_BST_ILIM_SHIFT 3