Lines Matching +full:1 +full:- +full:3
1 /* SPDX-License-Identifier: GPL-2.0-only */
19 * [20-19] : Op0
20 * [18-16] : Op1
21 * [15-12] : CRn
22 * [11-8] : CRm
23 * [7-5] : Op2
80 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
92 #define PSTATE_UAO pstate_field(0, 3)
93 #define PSTATE_SSBS pstate_field(3, 1)
94 #define PSTATE_TCO pstate_field(3, 4)
106 __emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f))
110 #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2)
111 #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2)
112 #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2)
121 #define SYS_OSDTRTX_EL1 sys_reg(2, 0, 0, 3, 2)
127 #define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0)
128 #define SYS_OSLAR_EL1 sys_reg(2, 0, 1, 0, 4)
129 #define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4)
130 #define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4)
131 #define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4)
135 #define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0)
136 #define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0)
137 #define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0)
138 #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0)
141 #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0)
142 #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
143 #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
145 #define SYS_ID_PFR0_EL1 sys_reg(3, 0, 0, 1, 0)
146 #define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1, 1)
147 #define SYS_ID_PFR2_EL1 sys_reg(3, 0, 0, 3, 4)
148 #define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2)
149 #define SYS_ID_DFR1_EL1 sys_reg(3, 0, 0, 3, 5)
150 #define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3)
151 #define SYS_ID_MMFR0_EL1 sys_reg(3, 0, 0, 1, 4)
152 #define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5)
153 #define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6)
154 #define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7)
155 #define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6)
156 #define SYS_ID_MMFR5_EL1 sys_reg(3, 0, 0, 3, 6)
158 #define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0)
159 #define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2, 1)
160 #define SYS_ID_ISAR2_EL1 sys_reg(3, 0, 0, 2, 2)
161 #define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3)
162 #define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4)
163 #define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5)
164 #define SYS_ID_ISAR6_EL1 sys_reg(3, 0, 0, 2, 7)
166 #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0)
167 #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1)
168 #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2)
170 #define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0)
171 #define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1)
172 #define SYS_ID_AA64ZFR0_EL1 sys_reg(3, 0, 0, 4, 4)
174 #define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0)
175 #define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1)
177 #define SYS_ID_AA64AFR0_EL1 sys_reg(3, 0, 0, 5, 4)
178 #define SYS_ID_AA64AFR1_EL1 sys_reg(3, 0, 0, 5, 5)
180 #define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0)
181 #define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1)
183 #define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0)
184 #define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1)
185 #define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2)
187 #define SYS_SCTLR_EL1 sys_reg(3, 0, 1, 0, 0)
188 #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1)
189 #define SYS_CPACR_EL1 sys_reg(3, 0, 1, 0, 2)
190 #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5)
191 #define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6)
193 #define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0)
194 #define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1)
196 #define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0)
197 #define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1)
198 #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2)
200 #define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0)
201 #define SYS_APIAKEYHI_EL1 sys_reg(3, 0, 2, 1, 1)
202 #define SYS_APIBKEYLO_EL1 sys_reg(3, 0, 2, 1, 2)
203 #define SYS_APIBKEYHI_EL1 sys_reg(3, 0, 2, 1, 3)
205 #define SYS_APDAKEYLO_EL1 sys_reg(3, 0, 2, 2, 0)
206 #define SYS_APDAKEYHI_EL1 sys_reg(3, 0, 2, 2, 1)
207 #define SYS_APDBKEYLO_EL1 sys_reg(3, 0, 2, 2, 2)
208 #define SYS_APDBKEYHI_EL1 sys_reg(3, 0, 2, 2, 3)
210 #define SYS_APGAKEYLO_EL1 sys_reg(3, 0, 2, 3, 0)
211 #define SYS_APGAKEYHI_EL1 sys_reg(3, 0, 2, 3, 1)
213 #define SYS_SPSR_EL1 sys_reg(3, 0, 4, 0, 0)
214 #define SYS_ELR_EL1 sys_reg(3, 0, 4, 0, 1)
216 #define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0)
218 #define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0)
219 #define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1)
220 #define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0)
222 #define SYS_ERRIDR_EL1 sys_reg(3, 0, 5, 3, 0)
223 #define SYS_ERRSELR_EL1 sys_reg(3, 0, 5, 3, 1)
224 #define SYS_ERXFR_EL1 sys_reg(3, 0, 5, 4, 0)
225 #define SYS_ERXCTLR_EL1 sys_reg(3, 0, 5, 4, 1)
226 #define SYS_ERXSTATUS_EL1 sys_reg(3, 0, 5, 4, 2)
227 #define SYS_ERXADDR_EL1 sys_reg(3, 0, 5, 4, 3)
228 #define SYS_ERXMISC0_EL1 sys_reg(3, 0, 5, 5, 0)
229 #define SYS_ERXMISC1_EL1 sys_reg(3, 0, 5, 5, 1)
230 #define SYS_TFSR_EL1 sys_reg(3, 0, 5, 6, 0)
231 #define SYS_TFSRE0_EL1 sys_reg(3, 0, 5, 6, 1)
233 #define SYS_FAR_EL1 sys_reg(3, 0, 6, 0, 0)
234 #define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0)
237 #define SYS_PAR_EL1_FST GENMASK(6, 1)
241 #define SYS_PMSIDR_EL1 sys_reg(3, 0, 9, 9, 7)
243 #define SYS_PMSIDR_EL1_FT_SHIFT 1
245 #define SYS_PMSIDR_EL1_ARCHINST_SHIFT 3
255 #define SYS_PMBIDR_EL1 sys_reg(3, 0, 9, 10, 7)
262 #define SYS_PMSCR_EL1 sys_reg(3, 0, 9, 9, 0)
264 #define SYS_PMSCR_EL1_E1SPE_SHIFT 1
265 #define SYS_PMSCR_EL1_CX_SHIFT 3
270 #define SYS_PMSCR_EL2 sys_reg(3, 4, 9, 9, 0)
272 #define SYS_PMSCR_EL2_E2SPE_SHIFT 1
273 #define SYS_PMSCR_EL2_CX_SHIFT 3
278 #define SYS_PMSICR_EL1 sys_reg(3, 0, 9, 9, 2)
280 #define SYS_PMSIRR_EL1 sys_reg(3, 0, 9, 9, 3)
286 #define SYS_PMSNEVFR_EL1 sys_reg(3, 0, 9, 9, 1)
288 #define SYS_PMSFCR_EL1 sys_reg(3, 0, 9, 9, 4)
290 #define SYS_PMSFCR_EL1_FT_SHIFT 1
296 #define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5)
303 #define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6)
307 #define SYS_PMBLIMITR_EL1 sys_reg(3, 0, 9, 10, 0)
309 #define SYS_PMBLIMITR_EL1_FM_SHIFT 1
313 #define SYS_PMBPTR_EL1 sys_reg(3, 0, 9, 10, 1)
316 #define SYS_PMBSR_EL1 sys_reg(3, 0, 9, 10, 3)
341 #define SYS_TRBLIMITR_EL1 sys_reg(3, 0, 9, 11, 0)
342 #define SYS_TRBPTR_EL1 sys_reg(3, 0, 9, 11, 1)
343 #define SYS_TRBBASER_EL1 sys_reg(3, 0, 9, 11, 2)
344 #define SYS_TRBSR_EL1 sys_reg(3, 0, 9, 11, 3)
345 #define SYS_TRBMAR_EL1 sys_reg(3, 0, 9, 11, 4)
346 #define SYS_TRBTRG_EL1 sys_reg(3, 0, 9, 11, 6)
347 #define SYS_TRBIDR_EL1 sys_reg(3, 0, 9, 11, 7)
352 #define TRBLIMITR_TRIG_MODE_MASK GENMASK(1, 0)
353 #define TRBLIMITR_TRIG_MODE_SHIFT 3
354 #define TRBLIMITR_FILL_MODE_MASK GENMASK(1, 0)
355 #define TRBLIMITR_FILL_MODE_SHIFT 1
374 #define TRBMAR_SHARE_MASK GENMASK(1, 0)
376 #define TRBMAR_OUTER_MASK GENMASK(3, 0)
378 #define TRBMAR_INNER_MASK GENMASK(3, 0)
384 #define TRBIDR_ALIGN_MASK GENMASK(3, 0)
387 #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1)
388 #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2)
390 #define SYS_PMMIR_EL1 sys_reg(3, 0, 9, 14, 6)
392 #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0)
393 #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0)
395 #define SYS_LORSA_EL1 sys_reg(3, 0, 10, 4, 0)
396 #define SYS_LOREA_EL1 sys_reg(3, 0, 10, 4, 1)
397 #define SYS_LORN_EL1 sys_reg(3, 0, 10, 4, 2)
398 #define SYS_LORC_EL1 sys_reg(3, 0, 10, 4, 3)
399 #define SYS_LORID_EL1 sys_reg(3, 0, 10, 4, 7)
401 #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0)
402 #define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1)
404 #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0)
405 #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1)
406 #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2)
407 #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3)
408 #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n)
410 #define SYS_ICC_AP0R1_EL1 SYS_ICC_AP0Rn_EL1(1)
412 #define SYS_ICC_AP0R3_EL1 SYS_ICC_AP0Rn_EL1(3)
413 #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n)
415 #define SYS_ICC_AP1R1_EL1 SYS_ICC_AP1Rn_EL1(1)
417 #define SYS_ICC_AP1R3_EL1 SYS_ICC_AP1Rn_EL1(3)
418 #define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1)
419 #define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3)
420 #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
421 #define SYS_ICC_ASGI1R_EL1 sys_reg(3, 0, 12, 11, 6)
422 #define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7)
423 #define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0)
424 #define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
425 #define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2)
426 #define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3)
427 #define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4)
428 #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
429 #define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6)
430 #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
432 #define SYS_CONTEXTIDR_EL1 sys_reg(3, 0, 13, 0, 1)
433 #define SYS_TPIDR_EL1 sys_reg(3, 0, 13, 0, 4)
435 #define SYS_SCXTNUM_EL1 sys_reg(3, 0, 13, 0, 7)
437 #define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0)
439 #define SYS_CCSIDR_EL1 sys_reg(3, 1, 0, 0, 0)
440 #define SYS_CLIDR_EL1 sys_reg(3, 1, 0, 0, 1)
441 #define SYS_GMID_EL1 sys_reg(3, 1, 0, 0, 4)
442 #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7)
444 #define SYS_CSSELR_EL1 sys_reg(3, 2, 0, 0, 0)
446 #define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1)
447 #define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7)
449 #define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0)
450 #define SYS_RNDRRS_EL0 sys_reg(3, 3, 2, 4, 1)
452 #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0)
453 #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1)
454 #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2)
455 #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3)
456 #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4)
457 #define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5)
458 #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6)
459 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7)
460 #define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0)
461 #define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1)
462 #define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2)
463 #define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0)
464 #define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3)
466 #define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2)
467 #define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3)
469 #define SYS_SCXTNUM_EL0 sys_reg(3, 3, 13, 0, 7)
472 #define SYS_AM_EL0(crm, op2) sys_reg(3, 3, 13, (crm), (op2))
474 #define SYS_AMCFGR_EL0 SYS_AM_EL0(2, 1)
476 #define SYS_AMUSERENR_EL0 SYS_AM_EL0(2, 3)
479 #define SYS_AMCNTENCLR1_EL0 SYS_AM_EL0(3, 0)
480 #define SYS_AMCNTENSET1_EL0 SYS_AM_EL0(3, 1)
485 * Counter: 11 011 1101 010:n<3> n<2:0>
486 * Type: 11 011 1101 011:n<3> n<2:0>
487 * n: 0-15
489 * Group 1 of activity monitors (auxiliary):
491 * Counter: 11 011 1101 110:n<3> n<2:0>
492 * Type: 11 011 1101 111:n<3> n<2:0>
493 * n: 0-15
496 #define SYS_AMEVCNTR0_EL0(n) SYS_AM_EL0(4 + ((n) >> 3), (n) & 7)
497 #define SYS_AMEVTYPER0_EL0(n) SYS_AM_EL0(6 + ((n) >> 3), (n) & 7)
498 #define SYS_AMEVCNTR1_EL0(n) SYS_AM_EL0(12 + ((n) >> 3), (n) & 7)
499 #define SYS_AMEVTYPER1_EL0(n) SYS_AM_EL0(14 + ((n) >> 3), (n) & 7)
503 #define SYS_AMEVCNTR0_CONST_EL0 SYS_AMEVCNTR0_EL0(1)
505 #define SYS_AMEVCNTR0_MEM_STALL SYS_AMEVCNTR0_EL0(3)
507 #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0)
509 #define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0)
510 #define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1)
511 #define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2)
513 #define SYS_CNTV_CTL_EL0 sys_reg(3, 3, 14, 3, 1)
514 #define SYS_CNTV_CVAL_EL0 sys_reg(3, 3, 14, 3, 2)
517 #define SYS_AARCH32_CNTP_CTL sys_reg(0, 0, 14, 2, 1)
521 #define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3))
522 #define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n))
523 #define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3))
524 #define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n))
526 #define SYS_PMCCFILTR_EL0 sys_reg(3, 3, 14, 15, 7)
528 #define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0)
529 #define SYS_HFGRTR_EL2 sys_reg(3, 4, 1, 1, 4)
530 #define SYS_HFGWTR_EL2 sys_reg(3, 4, 1, 1, 5)
531 #define SYS_HFGITR_EL2 sys_reg(3, 4, 1, 1, 6)
532 #define SYS_ZCR_EL2 sys_reg(3, 4, 1, 2, 0)
533 #define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1)
534 #define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0)
535 #define SYS_HDFGRTR_EL2 sys_reg(3, 4, 3, 1, 4)
536 #define SYS_HDFGWTR_EL2 sys_reg(3, 4, 3, 1, 5)
537 #define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6)
538 #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0)
539 #define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1)
540 #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1)
541 #define SYS_ESR_EL2 sys_reg(3, 4, 5, 2, 0)
542 #define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3)
543 #define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0)
544 #define SYS_TFSR_EL2 sys_reg(3, 4, 5, 6, 0)
545 #define SYS_FAR_EL2 sys_reg(3, 4, 6, 0, 0)
547 #define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1)
548 #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
550 #define SYS_ICH_AP0R1_EL2 __SYS__AP0Rx_EL2(1)
552 #define SYS_ICH_AP0R3_EL2 __SYS__AP0Rx_EL2(3)
554 #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
556 #define SYS_ICH_AP1R1_EL2 __SYS__AP1Rx_EL2(1)
558 #define SYS_ICH_AP1R3_EL2 __SYS__AP1Rx_EL2(3)
560 #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
561 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
562 #define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0)
563 #define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1)
564 #define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2)
565 #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
566 #define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5)
567 #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7)
569 #define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x)
571 #define SYS_ICH_LR1_EL2 __SYS__LR0_EL2(1)
573 #define SYS_ICH_LR3_EL2 __SYS__LR0_EL2(3)
579 #define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x)
581 #define SYS_ICH_LR9_EL2 __SYS__LR8_EL2(1)
583 #define SYS_ICH_LR11_EL2 __SYS__LR8_EL2(3)
589 /* VHE encodings for architectural EL0/1 system registers */
590 #define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0)
591 #define SYS_CPACR_EL12 sys_reg(3, 5, 1, 0, 2)
592 #define SYS_ZCR_EL12 sys_reg(3, 5, 1, 2, 0)
593 #define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0)
594 #define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1)
595 #define SYS_TCR_EL12 sys_reg(3, 5, 2, 0, 2)
596 #define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0)
597 #define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1)
598 #define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0)
599 #define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1)
600 #define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0)
601 #define SYS_TFSR_EL12 sys_reg(3, 5, 5, 6, 0)
602 #define SYS_FAR_EL12 sys_reg(3, 5, 6, 0, 0)
603 #define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0)
604 #define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0)
605 #define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0)
606 #define SYS_CONTEXTIDR_EL12 sys_reg(3, 5, 13, 0, 1)
607 #define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0)
608 #define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0)
609 #define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1)
610 #define SYS_CNTP_CVAL_EL02 sys_reg(3, 5, 14, 2, 2)
611 #define SYS_CNTV_TVAL_EL02 sys_reg(3, 5, 14, 3, 0)
612 #define SYS_CNTV_CTL_EL02 sys_reg(3, 5, 14, 3, 1)
613 #define SYS_CNTV_CVAL_EL02 sys_reg(3, 5, 14, 3, 2)
636 #define SCTLR_ELx_SA (BIT(3))
638 #define SCTLR_ELx_A (BIT(1))
803 #define ID_AA64PFR1_SSBS_PSTATE_ONLY 1
1098 #define SYS_TFSR_EL1_TF1_SHIFT 1
1099 #define SYS_TFSR_EL1_TF0 (UL(1) << SYS_TFSR_EL1_TF0_SHIFT)
1100 #define SYS_TFSR_EL1_TF1 (UL(1) << SYS_TFSR_EL1_TF1_SHIFT)
1109 #define TRFCR_EL2_CX BIT(3)
1110 #define TRFCR_ELx_ExTRE BIT(1)
1116 #define ICH_MISR_EOI (1 << 0)
1117 #define ICH_MISR_U (1 << 1)
1120 #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1)
1122 #define ICH_LR_EOI (1ULL << 41)
1123 #define ICH_LR_GROUP (1ULL << 60)
1124 #define ICH_LR_HW (1ULL << 61)
1125 #define ICH_LR_STATE (3ULL << 62)
1126 #define ICH_LR_PENDING_BIT (1ULL << 62)
1127 #define ICH_LR_ACTIVE_BIT (1ULL << 63)
1134 #define ICH_HCR_EN (1 << 0)
1135 #define ICH_HCR_UIE (1 << 1)
1136 #define ICH_HCR_NPIE (1 << 3)
1137 #define ICH_HCR_TC (1 << 10)
1138 #define ICH_HCR_TALL0 (1 << 11)
1139 #define ICH_HCR_TALL1 (1 << 12)
1145 #define ICH_VMCR_ACK_CTL_MASK (1 << ICH_VMCR_ACK_CTL_SHIFT)
1146 #define ICH_VMCR_FIQ_EN_SHIFT 3
1147 #define ICH_VMCR_FIQ_EN_MASK (1 << ICH_VMCR_FIQ_EN_SHIFT)
1149 #define ICH_VMCR_CBPR_MASK (1 << ICH_VMCR_CBPR_SHIFT)
1151 #define ICH_VMCR_EOIM_MASK (1 << ICH_VMCR_EOIM_SHIFT)
1159 #define ICH_VMCR_ENG0_MASK (1 << ICH_VMCR_ENG0_SHIFT)
1160 #define ICH_VMCR_ENG1_SHIFT 1
1161 #define ICH_VMCR_ENG1_MASK (1 << ICH_VMCR_ENG1_SHIFT)
1169 #define ICH_VTR_SEIS_MASK (1 << ICH_VTR_SEIS_SHIFT)
1171 #define ICH_VTR_A3V_MASK (1 << ICH_VTR_A3V_SHIFT)
1176 #define ARM64_FEATURE_MASK(x) (GENMASK_ULL(x##_SHIFT + ARM64_FEATURE_FIELD_BITS - 1, x##_SHIFT))
1180 .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
1200 " .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" \
1270 * set mask are set. Other bits are left as-is.