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/Linux-v5.15/arch/arm64/boot/dts/freescale/
Dimx8-ss-img.dtsi10 ranges = <0x58000000 0x0 0x58000000 0x1000000>;
14 #clock-cells = <0>;
20 reg = <0x58400000 0x00050000>;
39 reg = <0x58450000 0x00050000>;
59 reg = <0x585d0000 0x10000>;
71 reg = <0x585f0000 0x10000>;
/Linux-v5.15/Documentation/devicetree/bindings/pci/
Dfaraday,ftpci100.yaml18 The host controller appear on the PCI bus with vendor ID 0x159b (Faraday
19 Technology) and product ID 0x4321.
34 interrupt-map-mask = <0xf800 0 0 7>;
36 <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
37 <0x4800 0 0 2 &pci_intc 1>,
38 <0x4800 0 0 3 &pci_intc 2>,
39 <0x4800 0 0 4 &pci_intc 3>,
40 <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
41 <0x5000 0 0 2 &pci_intc 2>,
42 <0x5000 0 0 3 &pci_intc 3>,
[all …]
Dnvidia,tegra20-pcie.txt27 - cell 0 specifies the bus and device numbers of the root port:
30 - cell 1 denotes the upper 32 address bits and should be 0
45 - 0x81000000: I/O memory region
46 - 0x82000000: non-prefetchable memory region
47 - 0xc2000000: prefetchable memory region
73 - pinctrl-0: phandle for the default/active state of pin configurations.
104 - If lanes 0 to 3 are used:
150 - Root port 0 uses 4 lanes, root port 1 is unused.
158 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
171 reg = <0x80003000 0x00000800 /* PADS registers */
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/gpu/
Dnvidia,gk20a.txt46 reg = <0x0 0x57000000 0x0 0x01000000>,
47 <0x0 0x58000000 0x0 0x01000000>;
64 reg = <0x0 0x57000000 0x0 0x01000000>,
65 <0x0 0x58000000 0x0 0x01000000>;
82 reg = <0x0 0x17000000 0x0 0x1000000>,
83 <0x0 0x18000000 0x0 0x1000000>;
100 reg = <0x17000000 0x1000000>,
101 <0x18000000 0x1000000>;
/Linux-v5.15/arch/arm/boot/dts/
Dgemini.dtsi23 pinctrl-0 = <&pflash_default_pins>;
33 reg = <0x40000000 0x1000>;
41 offset = <0x0c>;
43 mask = <0xC0000000>;
51 pinctrl-0 = <&dram_default_pins>, <&system_default_pins>,
161 reg = <0x41000000 0x1000>;
170 reg = <0x42000000 0x100>;
175 pinctrl-0 = <&uart_default_pins>;
181 reg = <0x43000000 0x1000>;
195 reg = <0x45000000 0x100>;
[all …]
Domap5.dtsi45 #size-cells = <0>;
47 cpu0: cpu@0 {
50 reg = <0x0>;
69 reg = <0x1>;
115 reg = <0 0x40300000 0 0x20000>; /* 128k */
122 reg = <0 0x48211000 0 0x1000>,
123 <0 0x48212000 0 0x2000>,
124 <0 0x48214000 0 0x2000>,
125 <0 0x48216000 0 0x2000>;
133 reg = <0 0x48281000 0 0x1000>;
[all …]
Domap4.dtsi40 #size-cells = <0>;
42 cpu@0 {
46 reg = <0x0>;
57 reg = <0x1>;
67 reg = <0x40304000 0xa000>; /* 40k */
74 reg = <0x48241000 0x1000>,
75 <0x48240100 0x0100>;
81 reg = <0x48242000 0x1000>;
89 reg = <0x48240600 0x20>;
98 reg = <0x48281000 0x1000>;
[all …]
Ddra7.dtsi61 reg = <0x0 0x48211000 0x0 0x1000>,
62 <0x0 0x48212000 0x0 0x2000>,
63 <0x0 0x48214000 0x0 0x2000>,
64 <0x0 0x48216000 0x0 0x2000>;
73 reg = <0x0 0x48281000 0x0 0x1000>;
79 #size-cells = <0>;
81 cpu0: cpu@0 {
84 reg = <0>;
108 opp-supported-hw = <0xFF 0x01>;
117 opp-supported-hw = <0xFF 0x02>;
[all …]
Dstm32h743.dtsi54 #clock-cells = <0>;
56 clock-frequency = <0>;
60 #clock-cells = <0>;
66 #clock-cells = <0>;
68 clock-frequency = <0>;
75 reg = <0x40000c00 0x400>;
82 #size-cells = <0>;
84 reg = <0x40002400 0x400>;
95 trigger@0 {
97 reg = <0>;
[all …]
Dtegra20.dtsi17 memory@0 {
19 reg = <0 0>;
24 reg = <0x40000000 0x40000>;
27 ranges = <0 0x40000000 0x40000>;
30 reg = <0x400 0x3fc00>;
37 reg = <0x50000000 0x00024000>;
49 ranges = <0x54000000 0x54000000 0x04000000>;
53 reg = <0x54040000 0x00040000>;
62 reg = <0x54080000 0x00040000>;
71 reg = <0x540c0000 0x00040000>;
[all …]
/Linux-v5.15/arch/arm/mach-pxa/include/mach/
Daddr-map.h8 #define PXA_CS0_PHYS 0x00000000
9 #define PXA_CS1_PHYS 0x04000000
10 #define PXA_CS2_PHYS 0x08000000
11 #define PXA_CS3_PHYS 0x0C000000
12 #define PXA_CS4_PHYS 0x10000000
13 #define PXA_CS5_PHYS 0x14000000
15 #define PXA300_CS0_PHYS 0x00000000 /* PXA300/PXA310 _only_ */
16 #define PXA300_CS1_PHYS 0x30000000 /* PXA300/PXA310 _only_ */
17 #define PXA3xx_CS2_PHYS 0x10000000
18 #define PXA3xx_CS3_PHYS 0x14000000
[all …]
Dhardware.h19 #define UNCACHED_PHYS_0 0xfe000000
20 #define UNCACHED_PHYS_0_SIZE 0x00100000
25 * 0x40000000 - 0x41ffffff <--> 0xf2000000 - 0xf3ffffff
26 * 0x44000000 - 0x45ffffff <--> 0xf4000000 - 0xf5ffffff
27 * 0x48000000 - 0x49ffffff <--> 0xf6000000 - 0xf7ffffff
28 * 0x4c000000 - 0x4dffffff <--> 0xf8000000 - 0xf9ffffff
29 * 0x50000000 - 0x51ffffff <--> 0xfa000000 - 0xfbffffff
30 * 0x54000000 - 0x55ffffff <--> 0xfc000000 - 0xfdffffff
31 * 0x58000000 - 0x59ffffff <--> 0xfe000000 - 0xffffffff
36 #define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1))
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/memory-controllers/
Dnvidia,tegra20-mc.yaml48 const: 0
69 reg = <0x7000f000 0x400>, /* Controller registers */
70 <0x58000000 0x02000000>; /* GART aperture */
74 interrupts = <0 77 4>;
76 #iommu-cells = <0>;
/Linux-v5.15/arch/arm/mach-omap2/
Domap24xx.h19 #define L4_24XX_BASE 0x48000000
20 #define L4_WK_243X_BASE 0x49000000
21 #define L3_24XX_BASE 0x68000000
24 #define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000)
25 #define OMAP24XX_IVA_INTC_BASE 0x40000000
28 #define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000)
29 #define OMAP2420_PRCM_BASE (L4_24XX_BASE + 0x8000)
30 #define OMAP2420_CM_BASE (L4_24XX_BASE + 0x8000)
32 #define OMAP2420_SDRC_BASE (L3_24XX_BASE + 0x9000)
33 #define OMAP2420_SMS_BASE 0x68008000
[all …]
Diomap.h33 #define OMAP2_L3_IO_OFFSET 0x90000000
36 #define OMAP2_L4_IO_OFFSET 0xb2000000
39 #define OMAP4_L3_IO_OFFSET 0xb4000000
42 #define AM33XX_L4_WK_IO_OFFSET 0xb5000000
45 #define OMAP4_L3_PER_IO_OFFSET 0xb1100000
48 #define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */
58 #define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/
61 #define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */
65 #define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */
70 /* 0x6e000000 --> 0xfe000000 */
[all …]
/Linux-v5.15/arch/arm/mach-s3c/
Dmap-s3c24xx.h19 #define S3C2410_PA_IRQ (0x4A000000)
23 #define S3C2410_PA_MEMCTRL (0x48000000)
27 #define S3C2410_PA_TIMER (0x51000000)
34 #define S3C2410_PA_USBDEV (0x52000000)
38 #define S3C2410_PA_WATCHDOG (0x53000000)
52 #define S3C2410_PA_USBHOST (0x49000000)
55 #define S3C2416_PA_HSUDC (0x49800000)
59 #define S3C2410_PA_DMA (0x4B000000)
63 #define S3C2410_PA_CLKPWR (0x4C000000)
66 #define S3C2410_PA_LCD (0x4D000000)
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/display/ti/
Dti,omap-dss.txt50 reg = <0x58000000 0x80>;
61 reg = <0x58001000 0x1000>;
70 reg = <0x58006000 0x200>,
71 <0x58006200 0x100>,
72 <0x58006300 0x100>,
73 <0x58006400 0x1000>;
99 tfp410: encoder@0 {
101 gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; /* 0, power-down */
104 pinctrl-0 = <&tfp410_pins>;
108 #size-cells = <0>;
[all …]
/Linux-v5.15/drivers/net/wireless/mediatek/mt76/mt7915/
Dmmio.c37 { 0x54000000, 0x02000, 0x1000 }, /* WFDMA PCIE0 MCU DMA0 */ in __mt7915_reg_addr()
38 { 0x55000000, 0x03000, 0x1000 }, /* WFDMA PCIE0 MCU DMA1 */ in __mt7915_reg_addr()
39 { 0x58000000, 0x06000, 0x1000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */ in __mt7915_reg_addr()
40 { 0x59000000, 0x07000, 0x1000 }, /* WFDMA PCIE1 MCU DMA1 */ in __mt7915_reg_addr()
41 { 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */ in __mt7915_reg_addr()
42 { 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */ in __mt7915_reg_addr()
43 { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */ in __mt7915_reg_addr()
44 { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */ in __mt7915_reg_addr()
45 { 0x820c0000, 0x08000, 0x4000 }, /* WF_UMAC_TOP (PLE) */ in __mt7915_reg_addr()
46 { 0x820c8000, 0x0c000, 0x2000 }, /* WF_UMAC_TOP (PSE) */ in __mt7915_reg_addr()
[all …]
/Linux-v5.15/arch/nds32/kernel/
Dftrace.c22 unsigned long ip = (unsigned long)__builtin_return_address(0); in _mcount()
60 * first arg : __builtin_return_address(0) - MCOUNT_INSN_SIZE in _ftrace_caller()
64 "move $r1, %0 \n\t" in _ftrace_caller()
67 : "r" (parent_ip), "r" (__builtin_return_address(0))); in _ftrace_caller()
89 return 0; in ftrace_dyn_arch_init()
94 unsigned long opcode = 0x46000000; in gen_sethi_insn()
96 unsigned long rt_num = 0xf << 20; in gen_sethi_insn()
103 unsigned long opcode = 0x58000000; in gen_ori_insn()
104 unsigned long imm = addr & 0x0000fff; in gen_ori_insn()
105 unsigned long rt_num = 0xf << 20; in gen_ori_insn()
[all …]
/Linux-v5.15/drivers/gpu/drm/etnaviv/
Dcmdstream.xml.h7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
42 #define FE_OPCODE_LOAD_STATE 0x00000001
43 #define FE_OPCODE_END 0x00000002
44 #define FE_OPCODE_NOP 0x00000003
45 #define FE_OPCODE_DRAW_2D 0x00000004
46 #define FE_OPCODE_DRAW_PRIMITIVES 0x00000005
47 #define FE_OPCODE_DRAW_INDEXED_PRIMITIVES 0x00000006
48 #define FE_OPCODE_WAIT 0x00000007
49 #define FE_OPCODE_LINK 0x00000008
[all …]
/Linux-v5.15/drivers/net/wireless/mediatek/mt76/mt7921/
Ddma.c12 err = mt76_init_tx_queue(phy->mt76, 0, idx, n_desc, MT_TX_RING_BASE); in mt7921_init_tx_queues()
13 if (err < 0) in mt7921_init_tx_queues()
16 for (i = 0; i <= MT_TXQ_PSD; i++) in mt7921_init_tx_queues()
17 phy->mt76->q_tx[i] = phy->mt76->q_tx[0]; in mt7921_init_tx_queues()
19 return 0; in mt7921_init_tx_queues()
30 type = FIELD_GET(MT_RXD0_PKT_TYPE, le32_to_cpu(rxd[0])); in mt7921_queue_rx_skb()
31 flag = FIELD_GET(MT_RXD0_PKT_FLAG, le32_to_cpu(rxd[0])); in mt7921_queue_rx_skb()
33 if (type == PKT_TYPE_RX_EVENT && flag == 0x1) in mt7921_queue_rx_skb()
71 return 0; in mt7921_poll_tx()
79 return 0; in mt7921_poll_tx()
[all …]
/Linux-v5.15/drivers/gpu/drm/gma500/
Doaktrail_device.c33 return 0; in oaktrail_output_init()
42 #define MRST_BLC_MAX_PWM_REG_FREQ 0xFFFF
63 if (gma_power_begin(dev, 0)) { in oaktrail_set_brightness()
81 REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2))); in oaktrail_set_brightness()
86 return 0; in oaktrail_set_brightness()
122 REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2))); in device_backlight_init()
126 return 0; in device_backlight_init()
140 memset(&props, 0, sizeof(struct backlight_properties)); in oaktrail_backlight_init()
151 if (ret < 0) { in oaktrail_backlight_init()
159 return 0; in oaktrail_backlight_init()
[all …]
/Linux-v5.15/drivers/gpu/drm/savage/
Dsavage_drv.h101 S3_UNKNOWN = 0,
227 #define SAVAGE_FB_SIZE_S3 0x01000000 /* 16MB */
228 #define SAVAGE_FB_SIZE_S4 0x02000000 /* 32MB */
229 #define SAVAGE_MMIO_SIZE 0x00080000 /* 512kB */
230 #define SAVAGE_APERTURE_OFFSET 0x02000000 /* 32MB */
231 #define SAVAGE_APERTURE_SIZE 0x05000000 /* 5 tiled surfaces, 16MB each */
233 #define SAVAGE_BCI_OFFSET 0x00010000 /* offset of the BCI region
241 #define SAVAGE_STATUS_WORD0 0x48C00
242 #define SAVAGE_STATUS_WORD1 0x48C04
243 #define SAVAGE_ALT_STATUS_WORD0 0x48C60
[all …]
/Linux-v5.15/arch/arm64/boot/dts/nvidia/
Dtegra186.dtsi20 reg = <0x0 0x00100000 0x0 0xf000>,
21 <0x0 0x0010f000 0x0 0x1000>;
27 reg = <0x0 0x2200000 0x0 0x10000>,
28 <0x0 0x2210000 0x0 0x10000>;
44 reg = <0x0 0x02490000 0x0 0x10000>;
71 snps,burst-map = <0x7>;
85 ranges = <0x02900000 0x0 0x02900000 0x200000>;
90 reg = <0x02930000 0x20000>;
92 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
135 reg = <0x02a41000 0x1000>,
[all …]
/Linux-v5.15/crypto/
Daes_generic.c67 0xa56363c6, 0x847c7cf8, 0x997777ee, 0x8d7b7bf6,
68 0x0df2f2ff, 0xbd6b6bd6, 0xb16f6fde, 0x54c5c591,
69 0x50303060, 0x03010102, 0xa96767ce, 0x7d2b2b56,
70 0x19fefee7, 0x62d7d7b5, 0xe6abab4d, 0x9a7676ec,
71 0x45caca8f, 0x9d82821f, 0x40c9c989, 0x877d7dfa,
72 0x15fafaef, 0xeb5959b2, 0xc947478e, 0x0bf0f0fb,
73 0xecadad41, 0x67d4d4b3, 0xfda2a25f, 0xeaafaf45,
74 0xbf9c9c23, 0xf7a4a453, 0x967272e4, 0x5bc0c09b,
75 0xc2b7b775, 0x1cfdfde1, 0xae93933d, 0x6a26264c,
76 0x5a36366c, 0x413f3f7e, 0x02f7f7f5, 0x4fcccc83,
[all …]

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