33 	return 0;  in oaktrail_output_init()
42 #define MRST_BLC_MAX_PWM_REG_FREQ	    0xFFFF
63 	if (gma_power_begin(dev, 0)) {  in oaktrail_set_brightness()
81 		REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2)));  in oaktrail_set_brightness()
86 	return 0;  in oaktrail_set_brightness()
122 		REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2)));  in device_backlight_init()
126 	return 0;  in device_backlight_init()
140 	memset(&props, 0, sizeof(struct backlight_properties));  in oaktrail_backlight_init()
151 	if (ret < 0) {  in oaktrail_backlight_init()
159 	return 0;  in oaktrail_backlight_init()
180 	struct psb_pipe *p = &regs->pipe[0];  in oaktrail_save_display_registers()
220 	for (i = 0; i < 256; i++)  in oaktrail_save_display_registers()
259 		PSB_WVDC32(0, PP_CONTROL);  in oaktrail_save_display_registers()
263 		} while (pp_stat & 0x80000000);  in oaktrail_save_display_registers()
266 		PSB_WVDC32(0x58000000, DSPACNTR);  in oaktrail_save_display_registers()
268 		PSB_WVDC32(0, DSPASURF);  in oaktrail_save_display_registers()
274 		PSB_WVDC32(0x0, PIPEACONF);  in oaktrail_save_display_registers()
279 		PSB_WVDC32(0, MRST_DPLL_A);  in oaktrail_save_display_registers()
281 	return 0;  in oaktrail_save_display_registers()
294 	struct psb_pipe *p = &regs->pipe[0];  in oaktrail_restore_display_registers()
309 	PSB_WVDC32(0x80000000, VGACNTRL);  in oaktrail_restore_display_registers()
351 	for (i = 0; i < 256; i++)  in oaktrail_restore_display_registers()
373 	} while (pp_stat & 0x08000000);  in oaktrail_restore_display_registers()
378 	} while (pp_stat & 0x10000000);  in oaktrail_restore_display_registers()
396 	return 0;  in oaktrail_restore_display_registers()
421 	return 0;  in oaktrail_power_down()
441 		if ((pwr_sts & pwr_mask) == 0)  in oaktrail_power_up()
446 	return 0;  in oaktrail_power_up()
513 	if (ret < 0)  in oaktrail_chip_setup()
522 	return 0;  in oaktrail_chip_setup()
540 	.lvds_mask = (1 << 0),
542 	.cursor_needs_phys = 0,