12 	err = mt76_init_tx_queue(phy->mt76, 0, idx, n_desc, MT_TX_RING_BASE);  in mt7921_init_tx_queues()
13 	if (err < 0)  in mt7921_init_tx_queues()
16 	for (i = 0; i <= MT_TXQ_PSD; i++)  in mt7921_init_tx_queues()
17 		phy->mt76->q_tx[i] = phy->mt76->q_tx[0];  in mt7921_init_tx_queues()
19 	return 0;  in mt7921_init_tx_queues()
30 	type = FIELD_GET(MT_RXD0_PKT_TYPE, le32_to_cpu(rxd[0]));  in mt7921_queue_rx_skb()
31 	flag = FIELD_GET(MT_RXD0_PKT_FLAG, le32_to_cpu(rxd[0]));  in mt7921_queue_rx_skb()
33 	if (type == PKT_TYPE_RX_EVENT && flag == 0x1)  in mt7921_queue_rx_skb()
71 		return 0;  in mt7921_poll_tx()
79 	return 0;  in mt7921_poll_tx()
92 		return 0;  in mt7921_poll_rx()
104 	mt76_wr(dev, MT_WFDMA0_RX_RING0_EXT_CTRL, PREFETCH(0x0, 0x4));  in mt7921_dma_prefetch()
105 	mt76_wr(dev, MT_WFDMA0_RX_RING2_EXT_CTRL, PREFETCH(0x40, 0x4));  in mt7921_dma_prefetch()
106 	mt76_wr(dev, MT_WFDMA0_RX_RING3_EXT_CTRL, PREFETCH(0x80, 0x4));  in mt7921_dma_prefetch()
107 	mt76_wr(dev, MT_WFDMA0_RX_RING4_EXT_CTRL, PREFETCH(0xc0, 0x4));  in mt7921_dma_prefetch()
108 	mt76_wr(dev, MT_WFDMA0_RX_RING5_EXT_CTRL, PREFETCH(0x100, 0x4));  in mt7921_dma_prefetch()
110 	mt76_wr(dev, MT_WFDMA0_TX_RING0_EXT_CTRL, PREFETCH(0x140, 0x4));  in mt7921_dma_prefetch()
111 	mt76_wr(dev, MT_WFDMA0_TX_RING1_EXT_CTRL, PREFETCH(0x180, 0x4));  in mt7921_dma_prefetch()
112 	mt76_wr(dev, MT_WFDMA0_TX_RING2_EXT_CTRL, PREFETCH(0x1c0, 0x4));  in mt7921_dma_prefetch()
113 	mt76_wr(dev, MT_WFDMA0_TX_RING3_EXT_CTRL, PREFETCH(0x200, 0x4));  in mt7921_dma_prefetch()
114 	mt76_wr(dev, MT_WFDMA0_TX_RING4_EXT_CTRL, PREFETCH(0x240, 0x4));  in mt7921_dma_prefetch()
115 	mt76_wr(dev, MT_WFDMA0_TX_RING5_EXT_CTRL, PREFETCH(0x280, 0x4));  in mt7921_dma_prefetch()
116 	mt76_wr(dev, MT_WFDMA0_TX_RING6_EXT_CTRL, PREFETCH(0x2c0, 0x4));  in mt7921_dma_prefetch()
117 	mt76_wr(dev, MT_WFDMA0_TX_RING16_EXT_CTRL, PREFETCH(0x340, 0x4));  in mt7921_dma_prefetch()
118 	mt76_wr(dev, MT_WFDMA0_TX_RING17_EXT_CTRL, PREFETCH(0x380, 0x4));  in mt7921_dma_prefetch()
128 		{ 0x00400000, 0x80000, 0x10000}, /* WF_MCU_SYSRAM */  in __mt7921_reg_addr()
129 		{ 0x00410000, 0x90000, 0x10000}, /* WF_MCU_SYSRAM (configure register) */  in __mt7921_reg_addr()
130 		{ 0x40000000, 0x70000, 0x10000}, /* WF_UMAC_SYSRAM */  in __mt7921_reg_addr()
131 		{ 0x54000000, 0x02000, 0x1000 }, /* WFDMA PCIE0 MCU DMA0 */  in __mt7921_reg_addr()
132 		{ 0x55000000, 0x03000, 0x1000 }, /* WFDMA PCIE0 MCU DMA1 */  in __mt7921_reg_addr()
133 		{ 0x58000000, 0x06000, 0x1000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */  in __mt7921_reg_addr()
134 		{ 0x59000000, 0x07000, 0x1000 }, /* WFDMA PCIE1 MCU DMA1 */  in __mt7921_reg_addr()
135 		{ 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */  in __mt7921_reg_addr()
136 		{ 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */  in __mt7921_reg_addr()
137 		{ 0x7c060000, 0xe0000, 0x10000}, /* CONN_INFRA, conn_host_csr_top */  in __mt7921_reg_addr()
138 		{ 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */  in __mt7921_reg_addr()
139 		{ 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */  in __mt7921_reg_addr()
140 		{ 0x820c0000, 0x08000, 0x4000 }, /* WF_UMAC_TOP (PLE) */  in __mt7921_reg_addr()
141 		{ 0x820c8000, 0x0c000, 0x2000 }, /* WF_UMAC_TOP (PSE) */  in __mt7921_reg_addr()
142 		{ 0x820cc000, 0x0e000, 0x2000 }, /* WF_UMAC_TOP (PP) */  in __mt7921_reg_addr()
143 		{ 0x820ce000, 0x21c00, 0x0200 }, /* WF_LMAC_TOP (WF_SEC) */  in __mt7921_reg_addr()
144 		{ 0x820cf000, 0x22000, 0x1000 }, /* WF_LMAC_TOP (WF_PF) */  in __mt7921_reg_addr()
145 		{ 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */  in __mt7921_reg_addr()
146 		{ 0x820e0000, 0x20000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */  in __mt7921_reg_addr()
147 		{ 0x820e1000, 0x20400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */  in __mt7921_reg_addr()
148 		{ 0x820e2000, 0x20800, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */  in __mt7921_reg_addr()
149 		{ 0x820e3000, 0x20c00, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */  in __mt7921_reg_addr()
150 		{ 0x820e4000, 0x21000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */  in __mt7921_reg_addr()
151 		{ 0x820e5000, 0x21400, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */  in __mt7921_reg_addr()
152 		{ 0x820e7000, 0x21e00, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */  in __mt7921_reg_addr()
153 		{ 0x820e9000, 0x23400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */  in __mt7921_reg_addr()
154 		{ 0x820ea000, 0x24000, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */  in __mt7921_reg_addr()
155 		{ 0x820eb000, 0x24200, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */  in __mt7921_reg_addr()
156 		{ 0x820ec000, 0x24600, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_INT) */  in __mt7921_reg_addr()
157 		{ 0x820ed000, 0x24800, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */  in __mt7921_reg_addr()
158 		{ 0x820f0000, 0xa0000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */  in __mt7921_reg_addr()
159 		{ 0x820f1000, 0xa0600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */  in __mt7921_reg_addr()
160 		{ 0x820f2000, 0xa0800, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */  in __mt7921_reg_addr()
161 		{ 0x820f3000, 0xa0c00, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */  in __mt7921_reg_addr()
162 		{ 0x820f4000, 0xa1000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */  in __mt7921_reg_addr()
163 		{ 0x820f5000, 0xa1400, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */  in __mt7921_reg_addr()
164 		{ 0x820f7000, 0xa1e00, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */  in __mt7921_reg_addr()
165 		{ 0x820f9000, 0xa3400, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */  in __mt7921_reg_addr()
166 		{ 0x820fa000, 0xa4000, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */  in __mt7921_reg_addr()
167 		{ 0x820fb000, 0xa4200, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */  in __mt7921_reg_addr()
168 		{ 0x820fc000, 0xa4600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_INT) */  in __mt7921_reg_addr()
169 		{ 0x820fd000, 0xa4800, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */  in __mt7921_reg_addr()
173 	if (addr < 0x100000)  in __mt7921_reg_addr()
176 	for (i = 0; i < ARRAY_SIZE(fixed_map); i++) {  in __mt7921_reg_addr()
189 	if ((addr >= 0x18000000 && addr < 0x18c00000) ||  in __mt7921_reg_addr()
190 	    (addr >= 0x70000000 && addr < 0x78000000) ||  in __mt7921_reg_addr()
191 	    (addr >= 0x7c000000 && addr < 0x7c400000))  in __mt7921_reg_addr()
197 	return 0;  in __mt7921_reg_addr()
252 		       MT_WFDMA0_GLO_CFG_RX_DMA_BUSY, 0, 1000))  in mt7921_dma_disable()
255 	return 0;  in mt7921_dma_disable()
264 	mt76_wr(dev, MT_WFDMA0_RST_DTX_PTR, ~0);  in mt7921_dma_enable()
267 	mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG0, 0);  in mt7921_dma_enable()
288 	return 0;  in mt7921_dma_enable()
300 	for (i = 0; i < __MT_TXQ_MAX; i++)  in mt7921_dma_reset()
303 	for (i = 0; i < __MT_MCUQ_MAX; i++)  in mt7921_dma_reset()
324 	return 0;  in mt7921_wfsys_reset()
332 	for (i = 0; i < ARRAY_SIZE(dev->mt76.phy.q_tx); i++)  in mt7921_wpdma_reset()
335 	for (i = 0; i < ARRAY_SIZE(dev->mt76.q_mcu); i++)  in mt7921_wpdma_reset()
353 	return 0;  in mt7921_wpdma_reset()
364 		mt76_wr(dev, MT_WFDMA0_HOST_INT_ENA, 0);  in mt7921_wpdma_reinit_cond()
365 		mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0x0);  in mt7921_wpdma_reinit_cond()
374 		mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff);  in mt7921_wpdma_reinit_cond()
378 	return 0;  in mt7921_wpdma_reinit_cond()
413 	mt76_wr(dev, MT_WFDMA0_TX_RING0_EXT_CTRL, 0x4);  in mt7921_dma_init()
439 			       MT_RX_BUF_SIZE, MT_WFDMA0(0x540));  in mt7921_dma_init()
451 	if (ret < 0)  in mt7921_dma_init()