Lines Matching +full:0 +full:x58000000
20 reg = <0x0 0x00100000 0x0 0xf000>,
21 <0x0 0x0010f000 0x0 0x1000>;
27 reg = <0x0 0x2200000 0x0 0x10000>,
28 <0x0 0x2210000 0x0 0x10000>;
44 reg = <0x0 0x02490000 0x0 0x10000>;
71 snps,burst-map = <0x7>;
85 ranges = <0x02900000 0x0 0x02900000 0x200000>;
90 reg = <0x02930000 0x20000>;
92 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
135 reg = <0x02a41000 0x1000>,
136 <0x02a42000 0x2000>;
146 reg = <0x02900800 0x800>;
153 ranges = <0x02900800 0x02900800 0x11800>;
158 reg = <0x0290f000 0x1000>;
205 reg = <0x2901000 0x100>;
219 reg = <0x2901100 0x100>;
233 reg = <0x2901200 0x100>;
247 reg = <0x2901300 0x100>;
261 reg = <0x2901400 0x100>;
275 reg = <0x2901500 0x100>;
288 reg = <0x2904000 0x100>;
300 reg = <0x2904100 0x100>;
312 reg = <0x2904200 0x100>;
324 reg = <0x2904300 0x100>;
336 reg = <0x2905000 0x100>;
348 reg = <0x2905100 0x100>;
362 reg = <0x0 0x02c00000 0x0 0xb0000>;
370 ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>;
376 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
380 reg = <0x0 0x02c60000 0x0 0x50000>;
385 #interconnect-cells = <0>;
393 reg = <0x0 0x03100000 0x0 0x40>;
405 reg = <0x0 0x03110000 0x0 0x40>;
417 reg = <0x0 0x03130000 0x0 0x40>;
429 reg = <0x0 0x03140000 0x0 0x40>;
441 reg = <0x0 0x03150000 0x0 0x40>;
453 reg = <0x0 0x03160000 0x0 0x10000>;
456 #size-cells = <0>;
466 reg = <0x0 0x03180000 0x0 0x10000>;
469 #size-cells = <0>;
480 reg = <0x0 0x03190000 0x0 0x10000>;
483 #size-cells = <0>;
489 pinctrl-0 = <&state_dpaux1_i2c>;
497 reg = <0x0 0x031a0000 0x0 0x10000>;
500 #size-cells = <0>;
511 reg = <0x0 0x031b0000 0x0 0x10000>;
514 #size-cells = <0>;
520 pinctrl-0 = <&state_dpaux_i2c>;
527 reg = <0x0 0x031c0000 0x0 0x10000>;
530 #size-cells = <0>;
540 reg = <0x0 0x031e0000 0x0 0x10000>;
543 #size-cells = <0>;
553 reg = <0x0 0x3280000 0x0 0x10000>;
564 reg = <0x0 0x3290000 0x0 0x10000>;
575 reg = <0x0 0x32a0000 0x0 0x10000>;
586 reg = <0x0 0x32c0000 0x0 0x10000>;
597 reg = <0x0 0x32d0000 0x0 0x10000>;
608 reg = <0x0 0x32e0000 0x0 0x10000>;
619 reg = <0x0 0x32f0000 0x0 0x10000>;
630 reg = <0x0 0x03400000 0x0 0x10000>;
642 pinctrl-0 = <&sdmmc1_3v3>;
644 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
645 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
646 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
647 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
648 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>;
649 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>;
650 nvidia,default-tap = <0x5>;
651 nvidia,default-trim = <0xb>;
660 reg = <0x0 0x03420000 0x0 0x10000>;
672 pinctrl-0 = <&sdmmc2_3v3>;
674 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
675 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
676 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
677 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
678 nvidia,default-tap = <0x5>;
679 nvidia,default-trim = <0xb>;
685 reg = <0x0 0x03440000 0x0 0x10000>;
697 pinctrl-0 = <&sdmmc3_3v3>;
699 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
700 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
701 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
702 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
703 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
704 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
705 nvidia,default-tap = <0x5>;
706 nvidia,default-trim = <0xb>;
712 reg = <0x0 0x03460000 0x0 0x10000>;
726 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>;
727 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>;
728 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
729 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
730 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
731 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
732 nvidia,default-tap = <0x9>;
733 nvidia,default-trim = <0x5>;
742 reg = <0x0 0x03510000 0x0 0x10000>;
762 reg = <0x0 0x03520000 0x0 0x1000>,
763 <0x0 0x03540000 0x0 0x1000>;
779 usb2-0 {
781 #phy-cells = <0>;
786 #phy-cells = <0>;
791 #phy-cells = <0>;
802 hsic-0 {
804 #phy-cells = <0>;
813 usb3-0 {
815 #phy-cells = <0>;
820 #phy-cells = <0>;
825 #phy-cells = <0>;
832 usb2-0 {
844 hsic-0 {
848 usb3-0 {
864 reg = <0x0 0x03530000 0x0 0x8000>,
865 <0x0 0x03538000 0x0 0x1000>;
889 #size-cells = <0>;
897 reg = <0x0 0x03550000 0x0 0x8000>,
898 <0x0 0x03558000 0x0 0x1000>;
919 reg = <0x0 0x03820000 0x0 0x10000>;
928 reg = <0x0 0x03881000 0x0 0x1000>,
929 <0x0 0x03882000 0x0 0x2000>,
930 <0x0 0x03884000 0x0 0x2000>,
931 <0x0 0x03886000 0x0 0x2000>;
939 reg = <0x0 0x03960000 0x0 0x10000>;
948 reg = <0x0 0x03c00000 0x0 0xa0000>;
957 reg = <0x0 0x0c240000 0x0 0x10000>;
960 #size-cells = <0>;
970 reg = <0x0 0x0c250000 0x0 0x10000>;
973 #size-cells = <0>;
983 reg = <0x0 0x0c280000 0x0 0x40>;
995 reg = <0x0 0x0c290000 0x0 0x40>;
1007 reg = <0 0x0c2a0000 0 0x10000>;
1018 reg = <0x0 0xc2f0000 0x0 0x1000>,
1019 <0x0 0xc2f1000 0x0 0x1000>;
1029 reg = <0x0 0xc340000 0x0 0x10000>;
1040 reg = <0 0x0c360000 0 0x10000>,
1041 <0 0x0c370000 0 0x10000>,
1042 <0 0x0c380000 0 0x10000>,
1043 <0 0x0c390000 0 0x10000>;
1082 reg = <0x0 0x0e000000 0x0 0x3fffff>;
1091 reg = <0x0 0x10003000 0x0 0x00000800>, /* PADS registers */
1092 <0x0 0x10003800 0x0 0x00000800>, /* AFI registers */
1093 <0x0 0x40000000 0x0 0x10000000>; /* configuration space */
1101 interrupt-map-mask = <0 0 0 0>;
1102 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1104 bus-range = <0x00 0xff>;
1108 ranges = <0x02000000 0 0x10000000 0x0 0x10000000 0 0x00001000>, /* port 0 configuration space */
1109 <0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000>,/* port 1 configuration space */
1110 <0x02000000 0 0x10004000 0x0 0x10004000 0 0x00001000>, /* port 2 configuration space */
1111 <0x01000000 0 0x0 0x0 0x50000000 0 0x00010000>, /* downstream I/O (64 KiB) */
1112 <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */
1113 <0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
1130 iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>;
1131 iommu-map-mask = <0x0>;
1135 pci@1,0 {
1137 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
1138 reg = <0x000800 0 0 0 0>;
1148 pci@2,0 {
1150 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
1151 reg = <0x001000 0 0 0 0>;
1161 pci@3,0 {
1163 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
1164 reg = <0x001800 0 0 0 0>;
1177 reg = <0 0x12000000 0 0x800000>;
1243 stream-match-mask = <0x7f80>;
1252 reg = <0x0 0x13e00000 0x0 0x10000>,
1253 <0x0 0x13e10000 0x0 0x10000>;
1266 ranges = <0x15000000 0x0 0x15000000 0x01000000>;
1275 reg = <0x15040000 0x10000>;
1303 #size-cells = <0>;
1309 reg = <0x15200000 0x00040000>;
1330 ranges = <0x15200000 0x15200000 0x40000>;
1334 reg = <0x15200000 0x10000>;
1348 nvidia,head = <0>;
1353 reg = <0x15210000 0x10000>;
1372 reg = <0x15220000 0x10000>;
1392 reg = <0x15300000 0x10000>;
1407 reg = <0x15340000 0x40000>;
1423 reg = <0x15400000 0x10000>;
1438 reg = <0x15540000 0x10000>;
1450 pinctrl-0 = <&state_dpaux_aux>;
1457 nvidia,interface = <0>;
1462 reg = <0x15580000 0x10000>;
1474 pinctrl-0 = <&state_dpaux1_aux>;
1486 reg = <0x155c0000 0x10000>;
1514 #size-cells = <0>;
1520 reg = <0x15880000 0x10000>;
1528 reg = <0x15900000 0x10000>;
1543 reg = <0x15940000 0x10000>;
1559 reg = <0x0 0x17000000 0x0 0x1000000>,
1560 <0x0 0x18000000 0x0 0x1000000>;
1577 interconnect-names = "dma-mem", "write-0", "read-1", "write-1";
1582 reg = <0x0 0x30000000 0x0 0x50000>;
1585 ranges = <0x0 0x0 0x30000000 0x50000>;
1588 reg = <0x4e000 0x1000>;
1594 reg = <0x4f000 0x1000>;
1602 reg = <0x0 0x03507000 0x0 0x00002000>, /* AHCI */
1603 <0x0 0x03500000 0x0 0x00007000>, /* SATA */
1604 <0x0 0x03A90000 0x0 0x00010000>; /* SATA AUX */
1647 #size-cells = <0>;
1659 #size-cells = <0>;
1661 denver_0: cpu@0 {
1664 i-cache-size = <0x20000>;
1667 d-cache-size = <0x10000>;
1671 reg = <0x000>;
1677 i-cache-size = <0x20000>;
1680 d-cache-size = <0x10000>;
1684 reg = <0x001>;
1690 i-cache-size = <0xC000>;
1693 d-cache-size = <0x8000>;
1697 reg = <0x100>;
1703 i-cache-size = <0xC000>;
1706 d-cache-size = <0x8000>;
1710 reg = <0x101>;
1716 i-cache-size = <0xC000>;
1719 d-cache-size = <0x8000>;
1723 reg = <0x102>;
1729 i-cache-size = <0xC000>;
1732 d-cache-size = <0x8000>;
1736 reg = <0x103>;
1743 cache-size = <0x200000>;
1752 cache-size = <0x200000>;
1783 assigned-clock-parents = <0>,
1798 polling-delay = <0>;
1807 hysteresis = <0>;
1817 polling-delay = <0>;
1826 hysteresis = <0>;
1836 polling-delay = <0>;
1845 hysteresis = <0>;
1855 polling-delay = <0>;
1864 hysteresis = <0>;
1874 polling-delay = <0>;
1883 hysteresis = <0>;