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/Linux-v5.10/drivers/media/platform/qcom/venus/
Dhfi_cmds.h12 #define HFI_CMD_SYS_INIT 0x10001
13 #define HFI_CMD_SYS_PC_PREP 0x10002
14 #define HFI_CMD_SYS_SET_RESOURCE 0x10003
15 #define HFI_CMD_SYS_RELEASE_RESOURCE 0x10004
16 #define HFI_CMD_SYS_SET_PROPERTY 0x10005
17 #define HFI_CMD_SYS_GET_PROPERTY 0x10006
18 #define HFI_CMD_SYS_SESSION_INIT 0x10007
19 #define HFI_CMD_SYS_SESSION_END 0x10008
20 #define HFI_CMD_SYS_SET_BUFFERS 0x10009
21 #define HFI_CMD_SYS_TEST_SSR 0x10101
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/Linux-v5.10/Documentation/devicetree/bindings/arm/
Dcpus.yaml30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31 the reg property contained in bits 7 down to 0
49 this property is required and must be set to 0.
52 required and matches the CPUID[11:0] register bits.
54 Bits [11:0] in the reg cell must be set to
55 bits [11:0] in CPU ID register.
57 All other bits in the reg cell must be set to 0.
60 required and matches the CPU MPIDR[23:0] register
63 Bits [23:0] in the reg cell must be set to
64 bits [23:0] in MPIDR.
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Didle-states.yaml82 between 0 and infinite time, until a wake-up event occurs.
107 wakeup-delay = exit-latency + max(entry-latency - (now - entry-timestamp), 0)
147 0| 1 time(ms)
152 The graph curve with X-axis values = { x | 0 < x < 1ms } has a steep slope
332 #size-cells = <0>;
335 cpu@0 {
338 reg = <0x0 0x0>;
347 reg = <0x0 0x1>;
356 reg = <0x0 0x100>;
365 reg = <0x0 0x101>;
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/Linux-v5.10/Documentation/devicetree/bindings/cpu/
Dcpu-topology.txt87 (ie socket/cluster/core/thread) (where N = {0, 1, ...} is the node number; nodes
89 sequential N value, starting from 0).
187 #size-cells = <0>;
276 CPU0: cpu@0 {
279 reg = <0x0 0x0>;
281 cpu-release-addr = <0 0x20000000>;
287 reg = <0x0 0x1>;
289 cpu-release-addr = <0 0x20000000>;
295 reg = <0x0 0x100>;
297 cpu-release-addr = <0 0x20000000>;
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/Linux-v5.10/drivers/gpu/drm/xlnx/
Dzynqmp_disp_regs.h18 #define ZYNQMP_DISP_V_BLEND_BG_CLR_0 0x0
19 #define ZYNQMP_DISP_V_BLEND_BG_CLR_1 0x4
20 #define ZYNQMP_DISP_V_BLEND_BG_CLR_2 0x8
21 #define ZYNQMP_DISP_V_BLEND_BG_MAX 0xfff
22 #define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA 0xc
24 #define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_EN BIT(0)
25 #define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT 0x14
26 #define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_RGB 0x0
27 #define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR444 0x1
28 #define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR422 0x2
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/Linux-v5.10/drivers/scsi/qla2xxx/
Dqla_nx.h15 #define PHAN_INITIALIZE_FAILED 0xffff
16 #define PHAN_INITIALIZE_COMPLETE 0xff01
19 #define PHAN_INITIALIZE_ACK 0xf00f
20 #define PHAN_PEG_RCV_INITIALIZED 0xff01
23 #define QLA82XX_CRB_BASE QLA82XX_CAM_RAM(0x200)
26 #define CRB_CMDPEG_STATE QLA82XX_REG(0x50)
27 #define CRB_RCVPEG_STATE QLA82XX_REG(0x13c)
28 #define BOOT_LOADER_DIMM_STATUS QLA82XX_REG(0x54)
29 #define CRB_DMA_SHIFT QLA82XX_REG(0xcc)
30 #define CRB_TEMP_STATE QLA82XX_REG(0x1b4)
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/Linux-v5.10/arch/arm64/boot/dts/hisilicon/
Dhip06.dtsi23 #size-cells = <0>;
87 reg = <0x10000>;
95 reg = <0x10001>;
103 reg = <0x10002>;
111 reg = <0x10003>;
119 reg = <0x10100>;
127 reg = <0x10101>;
135 reg = <0x10102>;
143 reg = <0x10103>;
151 reg = <0x10200>;
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Dhip07.dtsi23 #size-cells = <0>;
270 reg = <0x10000>;
273 numa-node-id = <0>;
279 reg = <0x10001>;
282 numa-node-id = <0>;
288 reg = <0x10002>;
291 numa-node-id = <0>;
297 reg = <0x10003>;
300 numa-node-id = <0>;
306 reg = <0x10100>;
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/Linux-v5.10/drivers/gpu/drm/radeon/
Drv515.c50 0,
75 radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0)); in rv515_ring_start()
81 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); in rv515_ring_start()
83 radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0)); in rv515_ring_start()
85 radeon_ring_write(ring, PACKET0(GB_SELECT, 0)); in rv515_ring_start()
86 radeon_ring_write(ring, 0); in rv515_ring_start()
87 radeon_ring_write(ring, PACKET0(GB_ENABLE, 0)); in rv515_ring_start()
88 radeon_ring_write(ring, 0); in rv515_ring_start()
89 radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0)); in rv515_ring_start()
91 radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0)); in rv515_ring_start()
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/Linux-v5.10/Documentation/admin-guide/media/
Dvivid.rst63 hexadecimal values, one for each instance. The default is 0x1d3d.
66 - bit 0: Video Capture node
67 - bit 2-3: VBI Capture node: 0 = none, 1 = raw vbi, 2 = sliced vbi, 3 = both
71 - bit 10-11: VBI Output node: 0 = none, 1 = raw vbi, 2 = sliced vbi, 3 = both
84 n_devs=4 node_types=0x1,0x1,0x100,0x100
94 the input types for each instance, the default is 0xe4. This defines
97 pair gives the type and bits 0-1 map to input 0, bits 2-3 map to input 1,
105 So to create a video capture device with 8 inputs where input 0 is a TV
111 num_inputs=8 input_types=0xffa9
121 the output types for each instance, the default is 0x02. This defines
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