Lines Matching +full:0 +full:x10101
23 #size-cells = <0>;
270 reg = <0x10000>;
273 numa-node-id = <0>;
279 reg = <0x10001>;
282 numa-node-id = <0>;
288 reg = <0x10002>;
291 numa-node-id = <0>;
297 reg = <0x10003>;
300 numa-node-id = <0>;
306 reg = <0x10100>;
309 numa-node-id = <0>;
315 reg = <0x10101>;
318 numa-node-id = <0>;
324 reg = <0x10102>;
327 numa-node-id = <0>;
333 reg = <0x10103>;
336 numa-node-id = <0>;
342 reg = <0x10200>;
345 numa-node-id = <0>;
351 reg = <0x10201>;
354 numa-node-id = <0>;
360 reg = <0x10202>;
363 numa-node-id = <0>;
369 reg = <0x10203>;
372 numa-node-id = <0>;
378 reg = <0x10300>;
381 numa-node-id = <0>;
387 reg = <0x10301>;
390 numa-node-id = <0>;
396 reg = <0x10302>;
399 numa-node-id = <0>;
405 reg = <0x10303>;
408 numa-node-id = <0>;
414 reg = <0x30000>;
423 reg = <0x30001>;
432 reg = <0x30002>;
441 reg = <0x30003>;
450 reg = <0x30100>;
459 reg = <0x30101>;
468 reg = <0x30102>;
477 reg = <0x30103>;
486 reg = <0x30200>;
495 reg = <0x30201>;
504 reg = <0x30202>;
513 reg = <0x30203>;
522 reg = <0x30300>;
531 reg = <0x30301>;
540 reg = <0x30302>;
549 reg = <0x30303>;
558 reg = <0x50000>;
567 reg = <0x50001>;
576 reg = <0x50002>;
585 reg = <0x50003>;
594 reg = <0x50100>;
603 reg = <0x50101>;
612 reg = <0x50102>;
621 reg = <0x50103>;
630 reg = <0x50200>;
639 reg = <0x50201>;
648 reg = <0x50202>;
657 reg = <0x50203>;
666 reg = <0x50300>;
675 reg = <0x50301>;
684 reg = <0x50302>;
693 reg = <0x50303>;
702 reg = <0x70000>;
711 reg = <0x70001>;
720 reg = <0x70002>;
729 reg = <0x70003>;
738 reg = <0x70100>;
747 reg = <0x70101>;
756 reg = <0x70102>;
765 reg = <0x70103>;
774 reg = <0x70200>;
783 reg = <0x70201>;
792 reg = <0x70202>;
801 reg = <0x70203>;
810 reg = <0x70300>;
819 reg = <0x70301>;
828 reg = <0x70302>;
837 reg = <0x70303>;
916 redistributor-stride = <0x0 0x40000>;
917 reg = <0x0 0x4d000000 0x0 0x10000>, /* GICD */
918 <0x0 0x4d100000 0x0 0x400000>, /* p0 GICR node 0 */
919 <0x0 0x6d100000 0x0 0x400000>, /* p0 GICR node 1 */
920 <0x400 0x4d100000 0x0 0x400000>, /* p1 GICR node 2 */
921 <0x400 0x6d100000 0x0 0x400000>, /* p1 GICR node 3 */
922 <0x0 0xfe000000 0x0 0x10000>, /* GICC */
923 <0x0 0xfe010000 0x0 0x10000>, /* GICH */
924 <0x0 0xfe020000 0x0 0x10000>; /* GICV */
931 reg = <0x0 0x4c000000 0x0 0x40000>;
938 reg = <0x0 0x6c000000 0x0 0x40000>;
945 reg = <0x0 0xc6000000 0x0 0x40000>;
952 reg = <0x8 0xc6000000 0x0 0x40000>;
959 reg = <0x400 0x4c000000 0x0 0x40000>;
966 reg = <0x400 0x6c000000 0x0 0x40000>;
973 reg = <0x400 0xc6000000 0x0 0x40000>;
980 reg = <0x408 0xc6000000 0x0 0x40000>;
999 reg = <0x0 0x60080000 0x0 0x10000>;
1002 msi-parent = <&p0_its_peri_b 0x120c7>;
1011 reg = <0x0 0xa0080000 0x0 0x10000>;
1014 msi-parent = <&p0_its_dsa_a 0x40087>;
1021 msi-parent = <&p0_its_dsa_a 0x40000>;
1028 msi-parent = <&p0_its_dsa_a 0x40040>;
1035 msi-parent = <&p0_its_dsa_a 0x40b0c>;
1042 msi-parent = <&p0_its_dsa_a 0x40080>;
1050 reg = <0x0 0xd0080000 0x0 0x10000>;
1053 msi-parent = <&p0_its_dsa_a 0x40400>;
1059 msi-parent = <&p0_its_dsa_a 0x40b1b>;
1067 reg = <0x8 0xd0080000 0x0 0x10000>;
1070 msi-parent = <&p0_its_dsa_b 0x42400>;
1076 msi-parent = <&p0_its_dsa_b 0x42b1b>;
1084 reg = <0x400 0xd0080000 0x0 0x10000>;
1087 msi-parent = <&p1_its_dsa_a 0x44400>;
1093 msi-parent = <&p1_its_dsa_a 0x44b1b>;
1101 reg = <0x408 0xd0080000 0x0 0x10000>;
1104 msi-parent = <&p1_its_dsa_b 0x46400>;
1110 msi-parent = <&p1_its_dsa_b 0x46b1b>;
1118 reg = <0x0 0xc0080000 0x0 0x10000>;
1121 msi-parent = <&p0_its_dsa_a 0x40800>;
1128 msi-parent = <&p0_its_dsa_a 0x40B1E>;
1135 msi-parent = <&p0_its_dsa_a 0x40900>;
1142 msi-parent = <&p0_its_dsa_a 0x40b20>;
1166 reg = <0x0 0xa0040000 0x0 0x20000>;
1169 smmu-cb-memtype = <0x0 0x1>;
1175 reg = <0x0 0xd0040000 0x0 0x20000>;
1184 /* smmu-cb-memtype = <0x0 0x1>;*/
1188 reg = <0x8 0xd0040000 0x0 0x20000>;
1197 /* smmu-cb-memtype = <0x0 0x1>;*/
1201 reg = <0x400 0xd0040000 0x0 0x20000>;
1210 /* smmu-cb-memtype = <0x0 0x1>;*/
1214 reg = <0x408 0xd0040000 0x0 0x20000>;
1223 /* smmu-cb-memtype = <0x0 0x1>;*/
1236 reg = <0x0 0xa01b0000 0x0 0x1000>;
1241 reg = <0x01 0xe4 0x04>;
1248 reg = <0x0 0x602b0000 0x0 0x1000>;
1258 reg = <0x0 0xa7030000 0x0 0x10000>;
1267 reg = <0x0 0xa7020000 0x0 0x10000>;
1276 reg = <0 0x60000000 0x0 0x10000>;
1281 reg = <0x0 0xc0000000 0x0 0x10000>;
1286 reg = <0x0 0x78000010 0x0 0x100>;
1292 reg = <0x0 0xa0000000 0x0 0x10000>;
1297 reg = <0 0xc2200000 0x0 0x80000>;
1302 reg = <0x0 0x603c0000 0x0 0x1000>;
1303 subctrl-vbase = <&peri_c_subctrl 0x338 0xa38
1304 0x531c 0x5a1c>;
1306 #size-cells = <0>;
1308 phy0: ethernet-phy@0 {
1310 reg = <0>;
1321 #size-cells = <0>;
1324 reg = <0x0 0xc5000000 0x0 0x890000
1325 0x0 0xc7000000 0x0 0x600000>;
1329 reset-field-offset = <0>;
1414 desc-num = <0x400>;
1415 buf-size = <0x1000>;
1418 port@0 {
1419 reg = <0>;
1421 cpld-syscon = <&dsa_cpld 0x0>;
1422 port-rst-offset = <0>;
1423 port-mode-offset = <0>;
1431 cpld-syscon = <&dsa_cpld 0x4>;
1477 eth2: ethernet@0{
1480 port-idx-in-ae = <0>;
1497 reg = <0x0 0xc4000000 0x0 0x100000>;
1499 eth-handle = <ð2 ð3 0 0 ð0 ð1>;
1540 interrupt-names = "hns-roce-comp-0",
1578 reg = <0 0xc3000000 0 0x10000>;
1581 ctrl-reset-reg = <0xa60>;
1582 ctrl-reset-sts-reg = <0x5a30>;
1583 ctrl-clock-ena-reg = <0x338>;
1619 reg = <0 0xa2000000 0 0x10000>;
1623 ctrl-reset-reg = <0xa18>;
1624 ctrl-reset-sts-reg = <0x5a0c>;
1625 ctrl-clock-ena-reg = <0x318>;
1661 reg = <0 0xa3000000 0 0x10000>;
1664 ctrl-reset-reg = <0xae0>;
1665 ctrl-reset-sts-reg = <0x5a70>;
1666 ctrl-clock-ena-reg = <0x3a8>;
1702 reg = <0 0xaf800000 0 0x800000>,
1703 <0 0xa00a0000 0 0x10000>;
1704 bus-range = <0xf8 0xff>;
1705 msi-map = <0xf800 &p0_its_dsa_a 0xf800 0x800>;
1706 msi-map-mask = <0xffff>;
1711 ranges = <0x02000000 0 0xa8000000 0 0xa8000000 0 0x77f0000
1712 0x01000000 0 0 0 0xaf7f0000 0 0x10000>;
1714 interrupt-map-mask = <0xf800 0 0 7>;
1715 interrupt-map = <0x0 0 0 1 &mbigen_pcie2_a 671 4
1716 0x0 0 0 2 &mbigen_pcie2_a 671 4
1717 0x0 0 0 3 &mbigen_pcie2_a 671 4
1718 0x0 0 0 4 &mbigen_pcie2_a 671 4>;
1723 reg = <0x0 0xd0000000 0x0 0x10000
1724 0x0 0xd2000000 0x0 0x10000
1725 0x0 0xd2010000 0x0 0x10000
1726 0x0 0xd2020000 0x0 0x10000
1727 0x0 0xd2030000 0x0 0x10000
1728 0x0 0xd2040000 0x0 0x10000
1729 0x0 0xd2050000 0x0 0x10000
1730 0x0 0xd2060000 0x0 0x10000
1731 0x0 0xd2070000 0x0 0x10000
1732 0x0 0xd2080000 0x0 0x10000
1733 0x0 0xd2090000 0x0 0x10000
1734 0x0 0xd20a0000 0x0 0x10000
1735 0x0 0xd20b0000 0x0 0x10000
1736 0x0 0xd20c0000 0x0 0x10000
1737 0x0 0xd20d0000 0x0 0x10000
1738 0x0 0xd20e0000 0x0 0x10000
1739 0x0 0xd20f0000 0x0 0x10000
1740 0x0 0xd2100000 0x0 0x10000>;
1742 iommus = <&p0_smmu_alg_a 0x600>;
1764 reg = <0x8 0xd0000000 0x0 0x10000
1765 0x8 0xd2000000 0x0 0x10000
1766 0x8 0xd2010000 0x0 0x10000
1767 0x8 0xd2020000 0x0 0x10000
1768 0x8 0xd2030000 0x0 0x10000
1769 0x8 0xd2040000 0x0 0x10000
1770 0x8 0xd2050000 0x0 0x10000
1771 0x8 0xd2060000 0x0 0x10000
1772 0x8 0xd2070000 0x0 0x10000
1773 0x8 0xd2080000 0x0 0x10000
1774 0x8 0xd2090000 0x0 0x10000
1775 0x8 0xd20a0000 0x0 0x10000
1776 0x8 0xd20b0000 0x0 0x10000
1777 0x8 0xd20c0000 0x0 0x10000
1778 0x8 0xd20d0000 0x0 0x10000
1779 0x8 0xd20e0000 0x0 0x10000
1780 0x8 0xd20f0000 0x0 0x10000
1781 0x8 0xd2100000 0x0 0x10000>;
1783 iommus = <&p0_smmu_alg_b 0x600>;
1805 reg = <0x400 0xd0000000 0x0 0x10000
1806 0x400 0xd2000000 0x0 0x10000
1807 0x400 0xd2010000 0x0 0x10000
1808 0x400 0xd2020000 0x0 0x10000
1809 0x400 0xd2030000 0x0 0x10000
1810 0x400 0xd2040000 0x0 0x10000
1811 0x400 0xd2050000 0x0 0x10000
1812 0x400 0xd2060000 0x0 0x10000
1813 0x400 0xd2070000 0x0 0x10000
1814 0x400 0xd2080000 0x0 0x10000
1815 0x400 0xd2090000 0x0 0x10000
1816 0x400 0xd20a0000 0x0 0x10000
1817 0x400 0xd20b0000 0x0 0x10000
1818 0x400 0xd20c0000 0x0 0x10000
1819 0x400 0xd20d0000 0x0 0x10000
1820 0x400 0xd20e0000 0x0 0x10000
1821 0x400 0xd20f0000 0x0 0x10000
1822 0x400 0xd2100000 0x0 0x10000>;
1824 iommus = <&p1_smmu_alg_a 0x600>;
1846 reg = <0x408 0xd0000000 0x0 0x10000
1847 0x408 0xd2000000 0x0 0x10000
1848 0x408 0xd2010000 0x0 0x10000
1849 0x408 0xd2020000 0x0 0x10000
1850 0x408 0xd2030000 0x0 0x10000
1851 0x408 0xd2040000 0x0 0x10000
1852 0x408 0xd2050000 0x0 0x10000
1853 0x408 0xd2060000 0x0 0x10000
1854 0x408 0xd2070000 0x0 0x10000
1855 0x408 0xd2080000 0x0 0x10000
1856 0x408 0xd2090000 0x0 0x10000
1857 0x408 0xd20a0000 0x0 0x10000
1858 0x408 0xd20b0000 0x0 0x10000
1859 0x408 0xd20c0000 0x0 0x10000
1860 0x408 0xd20d0000 0x0 0x10000
1861 0x408 0xd20e0000 0x0 0x10000
1862 0x408 0xd20f0000 0x0 0x10000
1863 0x408 0xd2100000 0x0 0x10000>;
1865 iommus = <&p1_smmu_alg_b 0x600>;