Lines Matching +full:0 +full:x10101
23 #size-cells = <0>;
87 reg = <0x10000>;
95 reg = <0x10001>;
103 reg = <0x10002>;
111 reg = <0x10003>;
119 reg = <0x10100>;
127 reg = <0x10101>;
135 reg = <0x10102>;
143 reg = <0x10103>;
151 reg = <0x10200>;
159 reg = <0x10201>;
167 reg = <0x10202>;
175 reg = <0x10203>;
183 reg = <0x10300>;
191 reg = <0x10301>;
199 reg = <0x10302>;
207 reg = <0x10303>;
237 redistributor-stride = <0x0 0x30000>;
238 reg = <0x0 0x4d000000 0 0x10000>, /* GICD */
239 <0x0 0x4d100000 0 0x300000>, /* GICR */
240 <0x0 0xfe000000 0 0x10000>, /* GICC */
241 <0x0 0xfe010000 0 0x10000>, /* GICH */
242 <0x0 0xfe020000 0 0x10000>; /* GICV */
249 reg = <0x0 0xc6000000 0x0 0x40000>;
268 reg = <0x0 0xa0080000 0x0 0x10000>;
271 msi-parent = <&its_dsa 0x40080>;
278 msi-parent = <&its_dsa 0x40000>;
285 msi-parent = <&its_dsa 0x40040>;
292 msi-parent = <&its_dsa 0x40085>;
301 reg = <0x0 0xc0080000 0x0 0x10000>;
304 msi-parent = <&its_dsa 0x40800>;
311 msi-parent = <&its_dsa 0x40900>;
335 reg = <0x0 0xa0040000 0x0 0x20000>;
338 smmu-cb-memtype = <0x0 0x1>;
353 reg = <0x0 0xa01b0000 0x0 0x1000>;
358 reg = <0x01 0xe4 0x04>;
365 reg = <0x01 0x2f8 0x08>;
373 #clock-cells = <0>;
378 reg = <0x0 0xa7030000 0x0 0x10000>;
387 reg = <0x0 0xa7020000 0x0 0x10000>;
396 reg = <0 0x60000000 0x0 0x10000>;
401 reg = <0x0 0xc0000000 0x0 0x10000>;
406 reg = <0x0 0xa0000000 0x0 0x10000>;
411 reg = <0 0xc2200000 0x0 0x80000>;
416 reg = <0x0 0x603c0000 0x0 0x1000>;
417 subctrl-vbase = <&peri_c_subctrl 0x338 0xa38 0x531c 0x5a1c>;
419 #size-cells = <0>;
421 phy0: ethernet-phy@0 {
423 reg = <0>;
434 #size-cells = <0>;
437 reg = <0x0 0xc5000000 0x0 0x890000
438 0x0 0xc7000000 0x0 0x600000>;
442 reset-field-offset = <0>;
527 desc-num = <0x400>;
528 buf-size = <0x1000>;
531 port@0 {
532 reg = <0>;
534 port-rst-offset = <0>;
535 port-mode-offset = <0>;
584 eth2: ethernet-0{
587 port-idx-in-ae = <0>;
604 reg = <0 0xc3000000 0 0x10000>;
607 ctrl-reset-reg = <0xa60>;
608 ctrl-reset-sts-reg = <0x5a30>;
609 ctrl-clock-ena-reg = <0x338>;
610 clocks = <&refclk 0>;
646 reg = <0 0xa2000000 0 0x10000>;
650 ctrl-reset-reg = <0xa18>;
651 ctrl-reset-sts-reg = <0x5a0c>;
652 ctrl-clock-ena-reg = <0x318>;
653 clocks = <&refclk 0>;
689 reg = <0 0xa3000000 0 0x10000>;
692 ctrl-reset-reg = <0xae0>;
693 ctrl-reset-sts-reg = <0x5a70>;
694 ctrl-clock-ena-reg = <0x3a8>;
695 clocks = <&refclk 0>;
731 reg = <0 0xb0000000 0 0x2000000>,
732 <0 0xa0090000 0 0x10000>;
733 bus-range = <0 31>;
734 msi-map = <0x0000 &its_dsa 0x0000 0x2000>;
735 msi-map-mask = <0xffff>;
740 ranges = <0x02000000 0 0xb2000000 0x0 0xb2000000 0
741 0x5ff0000 0x01000000 0 0 0 0xb7ff0000
742 0 0x10000>;
744 interrupt-map-mask = <0xf800 0 0 7>;
745 interrupt-map = <0x0 0 0 1 &mbigen_pcie0 650 4
746 0x0 0 0 2 &mbigen_pcie0 650 4
747 0x0 0 0 3 &mbigen_pcie0 650 4
748 0x0 0 0 4 &mbigen_pcie0 650 4>;