Lines Matching +full:0 +full:x10101
50 0,
75 radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0)); in rv515_ring_start()
81 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); in rv515_ring_start()
83 radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0)); in rv515_ring_start()
85 radeon_ring_write(ring, PACKET0(GB_SELECT, 0)); in rv515_ring_start()
86 radeon_ring_write(ring, 0); in rv515_ring_start()
87 radeon_ring_write(ring, PACKET0(GB_ENABLE, 0)); in rv515_ring_start()
88 radeon_ring_write(ring, 0); in rv515_ring_start()
89 radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0)); in rv515_ring_start()
91 radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0)); in rv515_ring_start()
92 radeon_ring_write(ring, 0); in rv515_ring_start()
93 radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); in rv515_ring_start()
95 radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); in rv515_ring_start()
97 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); in rv515_ring_start()
99 radeon_ring_write(ring, PACKET0(GB_AA_CONFIG, 0)); in rv515_ring_start()
100 radeon_ring_write(ring, 0); in rv515_ring_start()
101 radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); in rv515_ring_start()
103 radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); in rv515_ring_start()
105 radeon_ring_write(ring, PACKET0(GB_MSPOS0, 0)); in rv515_ring_start()
115 radeon_ring_write(ring, PACKET0(GB_MSPOS1, 0)); in rv515_ring_start()
124 radeon_ring_write(ring, PACKET0(GA_ENHANCE, 0)); in rv515_ring_start()
126 radeon_ring_write(ring, PACKET0(GA_POLY_MODE, 0)); in rv515_ring_start()
128 radeon_ring_write(ring, PACKET0(GA_ROUND_MODE, 0)); in rv515_ring_start()
130 radeon_ring_write(ring, PACKET0(0x20C8, 0)); in rv515_ring_start()
131 radeon_ring_write(ring, 0); in rv515_ring_start()
140 for (i = 0; i < rdev->usec_timeout; i++) { in rv515_mc_wait_for_idle()
144 return 0; in rv515_mc_wait_for_idle()
170 (((gb_pipe_select >> 8) & 0xF) << 4); in rv515_gpu_init()
171 WREG32_PLL(0x000D, tmp); in rv515_gpu_init()
188 case 0: in rv515_vram_get_type()
205 radeon_vram_location(rdev, &rdev->mc, 0); in rv515_mc_init()
206 rdev->mc.gtt_base_align = 0; in rv515_mc_init()
218 WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff)); in rv515_mc_rreg()
220 WREG32(MC_IND_INDEX, 0); in rv515_mc_rreg()
231 WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff)); in rv515_mc_wreg()
233 WREG32(MC_IND_INDEX, 0); in rv515_mc_wreg()
246 seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); in rv515_debugfs_pipes_info()
248 seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp); in rv515_debugfs_pipes_info()
250 seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); in rv515_debugfs_pipes_info()
252 seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); in rv515_debugfs_pipes_info()
253 return 0; in rv515_debugfs_pipes_info()
263 tmp = RREG32(0x2140); in rv515_debugfs_ga_info()
264 seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp); in rv515_debugfs_ga_info()
266 tmp = RREG32(0x425C); in rv515_debugfs_ga_info()
267 seq_printf(m, "GA_IDLE 0x%08x\n", tmp); in rv515_debugfs_ga_info()
268 return 0; in rv515_debugfs_ga_info()
272 {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL},
276 {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL},
285 return 0; in rv515_debugfs_pipes_info_init()
294 return 0; in rv515_debugfs_ga_info_init()
307 WREG32(R_000300_VGA_RENDER_CONTROL, 0); in rv515_mc_stop()
309 for (i = 0; i < rdev->num_crtc; i++) { in rv515_mc_stop()
319 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0); in rv515_mc_stop()
323 for (j = 0; j < rdev->usec_timeout; j++) { in rv515_mc_stop()
334 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0); in rv515_mc_stop()
351 WREG32(R600_BIF_FB_EN, 0); in rv515_mc_stop()
364 for (i = 0; i < rdev->num_crtc; i++) { in rv515_mc_stop()
386 for (i = 0; i < rdev->num_crtc; i++) { in rv515_mc_resume()
388 if (i == 0) { in rv515_mc_resume()
408 for (i = 0; i < rdev->num_crtc; i++) { in rv515_mc_resume()
411 if ((tmp & 0x7) != 3) { in rv515_mc_resume()
412 tmp &= ~0x7; in rv515_mc_resume()
413 tmp |= 0x3; in rv515_mc_resume()
426 for (j = 0; j < rdev->usec_timeout; j++) { in rv515_mc_resume()
428 if ((tmp & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) == 0) in rv515_mc_resume()
450 for (i = 0; i < rdev->num_crtc; i++) { in rv515_mc_resume()
457 for (j = 0; j < rdev->usec_timeout; j++) { in rv515_mc_resume()
496 WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF); in rv515_mc_program()
497 WREG32_MC(R_000003_MC_AGP_BASE, 0); in rv515_mc_program()
498 WREG32_MC(R_000004_MC_AGP_BASE_2, 0); in rv515_mc_program()
567 return 0; in rv515_startup()
581 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", in rv515_resume()
608 return 0; in rv515_suspend()
661 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", in rv515_init()
709 return 0; in rv515_init()
714 int index_reg = 0x6578 + crtc->crtc_offset; in atom_rv515_force_tv_scaler()
715 int data_reg = 0x657c + crtc->crtc_offset; in atom_rv515_force_tv_scaler()
717 WREG32(0x659C + crtc->crtc_offset, 0x0); in atom_rv515_force_tv_scaler()
718 WREG32(0x6594 + crtc->crtc_offset, 0x705); in atom_rv515_force_tv_scaler()
719 WREG32(0x65A4 + crtc->crtc_offset, 0x10001); in atom_rv515_force_tv_scaler()
720 WREG32(0x65D8 + crtc->crtc_offset, 0x0); in atom_rv515_force_tv_scaler()
721 WREG32(0x65B0 + crtc->crtc_offset, 0x0); in atom_rv515_force_tv_scaler()
722 WREG32(0x65C0 + crtc->crtc_offset, 0x0); in atom_rv515_force_tv_scaler()
723 WREG32(0x65D4 + crtc->crtc_offset, 0x0); in atom_rv515_force_tv_scaler()
724 WREG32(index_reg, 0x0); in atom_rv515_force_tv_scaler()
725 WREG32(data_reg, 0x841880A8); in atom_rv515_force_tv_scaler()
726 WREG32(index_reg, 0x1); in atom_rv515_force_tv_scaler()
727 WREG32(data_reg, 0x84208680); in atom_rv515_force_tv_scaler()
728 WREG32(index_reg, 0x2); in atom_rv515_force_tv_scaler()
729 WREG32(data_reg, 0xBFF880B0); in atom_rv515_force_tv_scaler()
730 WREG32(index_reg, 0x100); in atom_rv515_force_tv_scaler()
731 WREG32(data_reg, 0x83D88088); in atom_rv515_force_tv_scaler()
732 WREG32(index_reg, 0x101); in atom_rv515_force_tv_scaler()
733 WREG32(data_reg, 0x84608680); in atom_rv515_force_tv_scaler()
734 WREG32(index_reg, 0x102); in atom_rv515_force_tv_scaler()
735 WREG32(data_reg, 0xBFF080D0); in atom_rv515_force_tv_scaler()
736 WREG32(index_reg, 0x200); in atom_rv515_force_tv_scaler()
737 WREG32(data_reg, 0x83988068); in atom_rv515_force_tv_scaler()
738 WREG32(index_reg, 0x201); in atom_rv515_force_tv_scaler()
739 WREG32(data_reg, 0x84A08680); in atom_rv515_force_tv_scaler()
740 WREG32(index_reg, 0x202); in atom_rv515_force_tv_scaler()
741 WREG32(data_reg, 0xBFF080F8); in atom_rv515_force_tv_scaler()
742 WREG32(index_reg, 0x300); in atom_rv515_force_tv_scaler()
743 WREG32(data_reg, 0x83588058); in atom_rv515_force_tv_scaler()
744 WREG32(index_reg, 0x301); in atom_rv515_force_tv_scaler()
745 WREG32(data_reg, 0x84E08660); in atom_rv515_force_tv_scaler()
746 WREG32(index_reg, 0x302); in atom_rv515_force_tv_scaler()
747 WREG32(data_reg, 0xBFF88120); in atom_rv515_force_tv_scaler()
748 WREG32(index_reg, 0x400); in atom_rv515_force_tv_scaler()
749 WREG32(data_reg, 0x83188040); in atom_rv515_force_tv_scaler()
750 WREG32(index_reg, 0x401); in atom_rv515_force_tv_scaler()
751 WREG32(data_reg, 0x85008660); in atom_rv515_force_tv_scaler()
752 WREG32(index_reg, 0x402); in atom_rv515_force_tv_scaler()
753 WREG32(data_reg, 0xBFF88150); in atom_rv515_force_tv_scaler()
754 WREG32(index_reg, 0x500); in atom_rv515_force_tv_scaler()
755 WREG32(data_reg, 0x82D88030); in atom_rv515_force_tv_scaler()
756 WREG32(index_reg, 0x501); in atom_rv515_force_tv_scaler()
757 WREG32(data_reg, 0x85408640); in atom_rv515_force_tv_scaler()
758 WREG32(index_reg, 0x502); in atom_rv515_force_tv_scaler()
759 WREG32(data_reg, 0xBFF88180); in atom_rv515_force_tv_scaler()
760 WREG32(index_reg, 0x600); in atom_rv515_force_tv_scaler()
761 WREG32(data_reg, 0x82A08018); in atom_rv515_force_tv_scaler()
762 WREG32(index_reg, 0x601); in atom_rv515_force_tv_scaler()
763 WREG32(data_reg, 0x85808620); in atom_rv515_force_tv_scaler()
764 WREG32(index_reg, 0x602); in atom_rv515_force_tv_scaler()
765 WREG32(data_reg, 0xBFF081B8); in atom_rv515_force_tv_scaler()
766 WREG32(index_reg, 0x700); in atom_rv515_force_tv_scaler()
767 WREG32(data_reg, 0x82608010); in atom_rv515_force_tv_scaler()
768 WREG32(index_reg, 0x701); in atom_rv515_force_tv_scaler()
769 WREG32(data_reg, 0x85A08600); in atom_rv515_force_tv_scaler()
770 WREG32(index_reg, 0x702); in atom_rv515_force_tv_scaler()
771 WREG32(data_reg, 0x800081F0); in atom_rv515_force_tv_scaler()
772 WREG32(index_reg, 0x800); in atom_rv515_force_tv_scaler()
773 WREG32(data_reg, 0x8228BFF8); in atom_rv515_force_tv_scaler()
774 WREG32(index_reg, 0x801); in atom_rv515_force_tv_scaler()
775 WREG32(data_reg, 0x85E085E0); in atom_rv515_force_tv_scaler()
776 WREG32(index_reg, 0x802); in atom_rv515_force_tv_scaler()
777 WREG32(data_reg, 0xBFF88228); in atom_rv515_force_tv_scaler()
778 WREG32(index_reg, 0x10000); in atom_rv515_force_tv_scaler()
779 WREG32(data_reg, 0x82A8BF00); in atom_rv515_force_tv_scaler()
780 WREG32(index_reg, 0x10001); in atom_rv515_force_tv_scaler()
781 WREG32(data_reg, 0x82A08CC0); in atom_rv515_force_tv_scaler()
782 WREG32(index_reg, 0x10002); in atom_rv515_force_tv_scaler()
783 WREG32(data_reg, 0x8008BEF8); in atom_rv515_force_tv_scaler()
784 WREG32(index_reg, 0x10100); in atom_rv515_force_tv_scaler()
785 WREG32(data_reg, 0x81F0BF28); in atom_rv515_force_tv_scaler()
786 WREG32(index_reg, 0x10101); in atom_rv515_force_tv_scaler()
787 WREG32(data_reg, 0x83608CA0); in atom_rv515_force_tv_scaler()
788 WREG32(index_reg, 0x10102); in atom_rv515_force_tv_scaler()
789 WREG32(data_reg, 0x8018BED0); in atom_rv515_force_tv_scaler()
790 WREG32(index_reg, 0x10200); in atom_rv515_force_tv_scaler()
791 WREG32(data_reg, 0x8148BF38); in atom_rv515_force_tv_scaler()
792 WREG32(index_reg, 0x10201); in atom_rv515_force_tv_scaler()
793 WREG32(data_reg, 0x84408C80); in atom_rv515_force_tv_scaler()
794 WREG32(index_reg, 0x10202); in atom_rv515_force_tv_scaler()
795 WREG32(data_reg, 0x8008BEB8); in atom_rv515_force_tv_scaler()
796 WREG32(index_reg, 0x10300); in atom_rv515_force_tv_scaler()
797 WREG32(data_reg, 0x80B0BF78); in atom_rv515_force_tv_scaler()
798 WREG32(index_reg, 0x10301); in atom_rv515_force_tv_scaler()
799 WREG32(data_reg, 0x85008C20); in atom_rv515_force_tv_scaler()
800 WREG32(index_reg, 0x10302); in atom_rv515_force_tv_scaler()
801 WREG32(data_reg, 0x8020BEA0); in atom_rv515_force_tv_scaler()
802 WREG32(index_reg, 0x10400); in atom_rv515_force_tv_scaler()
803 WREG32(data_reg, 0x8028BF90); in atom_rv515_force_tv_scaler()
804 WREG32(index_reg, 0x10401); in atom_rv515_force_tv_scaler()
805 WREG32(data_reg, 0x85E08BC0); in atom_rv515_force_tv_scaler()
806 WREG32(index_reg, 0x10402); in atom_rv515_force_tv_scaler()
807 WREG32(data_reg, 0x8018BE90); in atom_rv515_force_tv_scaler()
808 WREG32(index_reg, 0x10500); in atom_rv515_force_tv_scaler()
809 WREG32(data_reg, 0xBFB8BFB0); in atom_rv515_force_tv_scaler()
810 WREG32(index_reg, 0x10501); in atom_rv515_force_tv_scaler()
811 WREG32(data_reg, 0x86C08B40); in atom_rv515_force_tv_scaler()
812 WREG32(index_reg, 0x10502); in atom_rv515_force_tv_scaler()
813 WREG32(data_reg, 0x8010BE90); in atom_rv515_force_tv_scaler()
814 WREG32(index_reg, 0x10600); in atom_rv515_force_tv_scaler()
815 WREG32(data_reg, 0xBF58BFC8); in atom_rv515_force_tv_scaler()
816 WREG32(index_reg, 0x10601); in atom_rv515_force_tv_scaler()
817 WREG32(data_reg, 0x87A08AA0); in atom_rv515_force_tv_scaler()
818 WREG32(index_reg, 0x10602); in atom_rv515_force_tv_scaler()
819 WREG32(data_reg, 0x8010BE98); in atom_rv515_force_tv_scaler()
820 WREG32(index_reg, 0x10700); in atom_rv515_force_tv_scaler()
821 WREG32(data_reg, 0xBF10BFF0); in atom_rv515_force_tv_scaler()
822 WREG32(index_reg, 0x10701); in atom_rv515_force_tv_scaler()
823 WREG32(data_reg, 0x886089E0); in atom_rv515_force_tv_scaler()
824 WREG32(index_reg, 0x10702); in atom_rv515_force_tv_scaler()
825 WREG32(data_reg, 0x8018BEB0); in atom_rv515_force_tv_scaler()
826 WREG32(index_reg, 0x10800); in atom_rv515_force_tv_scaler()
827 WREG32(data_reg, 0xBED8BFE8); in atom_rv515_force_tv_scaler()
828 WREG32(index_reg, 0x10801); in atom_rv515_force_tv_scaler()
829 WREG32(data_reg, 0x89408940); in atom_rv515_force_tv_scaler()
830 WREG32(index_reg, 0x10802); in atom_rv515_force_tv_scaler()
831 WREG32(data_reg, 0xBFE8BED8); in atom_rv515_force_tv_scaler()
832 WREG32(index_reg, 0x20000); in atom_rv515_force_tv_scaler()
833 WREG32(data_reg, 0x80008000); in atom_rv515_force_tv_scaler()
834 WREG32(index_reg, 0x20001); in atom_rv515_force_tv_scaler()
835 WREG32(data_reg, 0x90008000); in atom_rv515_force_tv_scaler()
836 WREG32(index_reg, 0x20002); in atom_rv515_force_tv_scaler()
837 WREG32(data_reg, 0x80008000); in atom_rv515_force_tv_scaler()
838 WREG32(index_reg, 0x20003); in atom_rv515_force_tv_scaler()
839 WREG32(data_reg, 0x80008000); in atom_rv515_force_tv_scaler()
840 WREG32(index_reg, 0x20100); in atom_rv515_force_tv_scaler()
841 WREG32(data_reg, 0x80108000); in atom_rv515_force_tv_scaler()
842 WREG32(index_reg, 0x20101); in atom_rv515_force_tv_scaler()
843 WREG32(data_reg, 0x8FE0BF70); in atom_rv515_force_tv_scaler()
844 WREG32(index_reg, 0x20102); in atom_rv515_force_tv_scaler()
845 WREG32(data_reg, 0xBFE880C0); in atom_rv515_force_tv_scaler()
846 WREG32(index_reg, 0x20103); in atom_rv515_force_tv_scaler()
847 WREG32(data_reg, 0x80008000); in atom_rv515_force_tv_scaler()
848 WREG32(index_reg, 0x20200); in atom_rv515_force_tv_scaler()
849 WREG32(data_reg, 0x8018BFF8); in atom_rv515_force_tv_scaler()
850 WREG32(index_reg, 0x20201); in atom_rv515_force_tv_scaler()
851 WREG32(data_reg, 0x8F80BF08); in atom_rv515_force_tv_scaler()
852 WREG32(index_reg, 0x20202); in atom_rv515_force_tv_scaler()
853 WREG32(data_reg, 0xBFD081A0); in atom_rv515_force_tv_scaler()
854 WREG32(index_reg, 0x20203); in atom_rv515_force_tv_scaler()
855 WREG32(data_reg, 0xBFF88000); in atom_rv515_force_tv_scaler()
856 WREG32(index_reg, 0x20300); in atom_rv515_force_tv_scaler()
857 WREG32(data_reg, 0x80188000); in atom_rv515_force_tv_scaler()
858 WREG32(index_reg, 0x20301); in atom_rv515_force_tv_scaler()
859 WREG32(data_reg, 0x8EE0BEC0); in atom_rv515_force_tv_scaler()
860 WREG32(index_reg, 0x20302); in atom_rv515_force_tv_scaler()
861 WREG32(data_reg, 0xBFB082A0); in atom_rv515_force_tv_scaler()
862 WREG32(index_reg, 0x20303); in atom_rv515_force_tv_scaler()
863 WREG32(data_reg, 0x80008000); in atom_rv515_force_tv_scaler()
864 WREG32(index_reg, 0x20400); in atom_rv515_force_tv_scaler()
865 WREG32(data_reg, 0x80188000); in atom_rv515_force_tv_scaler()
866 WREG32(index_reg, 0x20401); in atom_rv515_force_tv_scaler()
867 WREG32(data_reg, 0x8E00BEA0); in atom_rv515_force_tv_scaler()
868 WREG32(index_reg, 0x20402); in atom_rv515_force_tv_scaler()
869 WREG32(data_reg, 0xBF8883C0); in atom_rv515_force_tv_scaler()
870 WREG32(index_reg, 0x20403); in atom_rv515_force_tv_scaler()
871 WREG32(data_reg, 0x80008000); in atom_rv515_force_tv_scaler()
872 WREG32(index_reg, 0x20500); in atom_rv515_force_tv_scaler()
873 WREG32(data_reg, 0x80188000); in atom_rv515_force_tv_scaler()
874 WREG32(index_reg, 0x20501); in atom_rv515_force_tv_scaler()
875 WREG32(data_reg, 0x8D00BE90); in atom_rv515_force_tv_scaler()
876 WREG32(index_reg, 0x20502); in atom_rv515_force_tv_scaler()
877 WREG32(data_reg, 0xBF588500); in atom_rv515_force_tv_scaler()
878 WREG32(index_reg, 0x20503); in atom_rv515_force_tv_scaler()
879 WREG32(data_reg, 0x80008008); in atom_rv515_force_tv_scaler()
880 WREG32(index_reg, 0x20600); in atom_rv515_force_tv_scaler()
881 WREG32(data_reg, 0x80188000); in atom_rv515_force_tv_scaler()
882 WREG32(index_reg, 0x20601); in atom_rv515_force_tv_scaler()
883 WREG32(data_reg, 0x8BC0BE98); in atom_rv515_force_tv_scaler()
884 WREG32(index_reg, 0x20602); in atom_rv515_force_tv_scaler()
885 WREG32(data_reg, 0xBF308660); in atom_rv515_force_tv_scaler()
886 WREG32(index_reg, 0x20603); in atom_rv515_force_tv_scaler()
887 WREG32(data_reg, 0x80008008); in atom_rv515_force_tv_scaler()
888 WREG32(index_reg, 0x20700); in atom_rv515_force_tv_scaler()
889 WREG32(data_reg, 0x80108000); in atom_rv515_force_tv_scaler()
890 WREG32(index_reg, 0x20701); in atom_rv515_force_tv_scaler()
891 WREG32(data_reg, 0x8A80BEB0); in atom_rv515_force_tv_scaler()
892 WREG32(index_reg, 0x20702); in atom_rv515_force_tv_scaler()
893 WREG32(data_reg, 0xBF0087C0); in atom_rv515_force_tv_scaler()
894 WREG32(index_reg, 0x20703); in atom_rv515_force_tv_scaler()
895 WREG32(data_reg, 0x80008008); in atom_rv515_force_tv_scaler()
896 WREG32(index_reg, 0x20800); in atom_rv515_force_tv_scaler()
897 WREG32(data_reg, 0x80108000); in atom_rv515_force_tv_scaler()
898 WREG32(index_reg, 0x20801); in atom_rv515_force_tv_scaler()
899 WREG32(data_reg, 0x8920BED0); in atom_rv515_force_tv_scaler()
900 WREG32(index_reg, 0x20802); in atom_rv515_force_tv_scaler()
901 WREG32(data_reg, 0xBED08920); in atom_rv515_force_tv_scaler()
902 WREG32(index_reg, 0x20803); in atom_rv515_force_tv_scaler()
903 WREG32(data_reg, 0x80008010); in atom_rv515_force_tv_scaler()
904 WREG32(index_reg, 0x30000); in atom_rv515_force_tv_scaler()
905 WREG32(data_reg, 0x90008000); in atom_rv515_force_tv_scaler()
906 WREG32(index_reg, 0x30001); in atom_rv515_force_tv_scaler()
907 WREG32(data_reg, 0x80008000); in atom_rv515_force_tv_scaler()
908 WREG32(index_reg, 0x30100); in atom_rv515_force_tv_scaler()
909 WREG32(data_reg, 0x8FE0BF90); in atom_rv515_force_tv_scaler()
910 WREG32(index_reg, 0x30101); in atom_rv515_force_tv_scaler()
911 WREG32(data_reg, 0xBFF880A0); in atom_rv515_force_tv_scaler()
912 WREG32(index_reg, 0x30200); in atom_rv515_force_tv_scaler()
913 WREG32(data_reg, 0x8F60BF40); in atom_rv515_force_tv_scaler()
914 WREG32(index_reg, 0x30201); in atom_rv515_force_tv_scaler()
915 WREG32(data_reg, 0xBFE88180); in atom_rv515_force_tv_scaler()
916 WREG32(index_reg, 0x30300); in atom_rv515_force_tv_scaler()
917 WREG32(data_reg, 0x8EC0BF00); in atom_rv515_force_tv_scaler()
918 WREG32(index_reg, 0x30301); in atom_rv515_force_tv_scaler()
919 WREG32(data_reg, 0xBFC88280); in atom_rv515_force_tv_scaler()
920 WREG32(index_reg, 0x30400); in atom_rv515_force_tv_scaler()
921 WREG32(data_reg, 0x8DE0BEE0); in atom_rv515_force_tv_scaler()
922 WREG32(index_reg, 0x30401); in atom_rv515_force_tv_scaler()
923 WREG32(data_reg, 0xBFA083A0); in atom_rv515_force_tv_scaler()
924 WREG32(index_reg, 0x30500); in atom_rv515_force_tv_scaler()
925 WREG32(data_reg, 0x8CE0BED0); in atom_rv515_force_tv_scaler()
926 WREG32(index_reg, 0x30501); in atom_rv515_force_tv_scaler()
927 WREG32(data_reg, 0xBF7884E0); in atom_rv515_force_tv_scaler()
928 WREG32(index_reg, 0x30600); in atom_rv515_force_tv_scaler()
929 WREG32(data_reg, 0x8BA0BED8); in atom_rv515_force_tv_scaler()
930 WREG32(index_reg, 0x30601); in atom_rv515_force_tv_scaler()
931 WREG32(data_reg, 0xBF508640); in atom_rv515_force_tv_scaler()
932 WREG32(index_reg, 0x30700); in atom_rv515_force_tv_scaler()
933 WREG32(data_reg, 0x8A60BEE8); in atom_rv515_force_tv_scaler()
934 WREG32(index_reg, 0x30701); in atom_rv515_force_tv_scaler()
935 WREG32(data_reg, 0xBF2087A0); in atom_rv515_force_tv_scaler()
936 WREG32(index_reg, 0x30800); in atom_rv515_force_tv_scaler()
937 WREG32(data_reg, 0x8900BF00); in atom_rv515_force_tv_scaler()
938 WREG32(index_reg, 0x30801); in atom_rv515_force_tv_scaler()
939 WREG32(data_reg, 0xBF008900); in atom_rv515_force_tv_scaler()
1245 if (rdev->mode_info.crtcs[0]->base.enabled) in rv515_bandwidth_avivo_update()
1246 mode0 = &rdev->mode_info.crtcs[0]->base.mode; in rv515_bandwidth_avivo_update()
1251 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false); in rv515_bandwidth_avivo_update()
1254 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, false); in rv515_bandwidth_avivo_update()
1287 if (rdev->mode_info.crtcs[0]->base.enabled) in rv515_bandwidth_update()
1288 mode0 = &rdev->mode_info.crtcs[0]->base.mode; in rv515_bandwidth_update()