Searched +full:0 +full:x10060000 (Results 1 – 19 of 19) sorted by relevance
/Linux-v6.1/Documentation/devicetree/bindings/gpio/ |
D | sifive,gpio.yaml | 85 reg = <0x10060000 0x1000>;
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/Linux-v6.1/Documentation/devicetree/bindings/thermal/ |
D | samsung,exynos-thermal.yaml | 24 # For TMU channel 0, 1 on Exynos5420: 59 TRIMINFO at 0x1006c000 contains data for TMU channel 3 60 TRIMINFO at 0x100a0000 contains data for TMU channel 4 61 TRIMINFO at 0x10068000 contains data for TMU channel 2 150 reg = <0x100C0000 0x100>; 153 #thermal-sensor-cells = <0>; 164 reg = <0x10068000 0x100>, <0x1006c000 0x4>; 166 #thermal-sensor-cells = <0>; 177 reg = <0x10060000 0x200>; 179 #thermal-sensor-cells = <0>;
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/Linux-v6.1/arch/arm64/boot/dts/mediatek/ |
D | mt7986a.dtsi | 17 clk40m: oscillator@0 { 20 #clock-cells = <0>; 26 #size-cells = <0>; 27 cpu0: cpu@0 { 31 reg = <0x0>; 39 reg = <0x1>; 47 reg = <0x2>; 55 reg = <0x3>; 71 reg = <0 0x43000000 0 0x30000>; 77 reg = <0 0x4fc00000 0 0x00100000>; [all …]
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/Linux-v6.1/arch/riscv/boot/dts/sifive/ |
D | fu540-c000.dtsi | 24 #size-cells = <0>; 25 cpu0: cpu@0 { 31 reg = <0>; 167 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; 168 reg = <0x0 0xc000000 0x0 0x4000000>; 169 #address-cells = <0>; 173 <&cpu0_intc 0xffffffff>, 174 <&cpu1_intc 0xffffffff>, <&cpu1_intc 9>, 175 <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>, 176 <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>, [all …]
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D | fu740-c000.dtsi | 24 #size-cells = <0>; 25 cpu0: cpu@0 { 32 reg = <0x0>; 56 reg = <0x1>; 80 reg = <0x2>; 104 reg = <0x3>; 128 reg = <0x4>; 169 #address-cells = <0>; 170 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; 171 reg = <0x0 0xc000000 0x0 0x4000000>; [all …]
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/Linux-v6.1/arch/arm/boot/dts/ |
D | exynos5410.dtsi | 31 #size-cells = <0>; 33 cpu0: cpu@0 { 36 reg = <0x0>; 43 reg = <0x1>; 50 reg = <0x2>; 57 reg = <0x3>; 70 reg = <0x10040000 0x5000>; 78 reg = <0x10010000 0x30000>; 84 reg = <0x03810000 0x0C>; 92 reg = <0x10060000 0x100>; [all …]
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D | exynos4210.dtsi | 33 #size-cells = <0>; 49 reg = <0x900>; 68 reg = <0x901>; 88 reg = <0x02020000 0x20000>; 91 ranges = <0 0x02020000 0x20000>; 93 smp-sram@0 { 95 reg = <0x0 0x1000>; 100 reg = <0x1f000 0x1000>; 106 reg = <0x10023CA0 0x20>; 107 #power-domain-cells = <0>; [all …]
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D | exynos4412.dtsi | 36 #size-cells = <0>; 58 reg = <0xA00>; 68 reg = <0xA01>; 78 reg = <0xA02>; 88 reg = <0xA03>; 179 reg = <0x11400000 0x1000>; 185 reg = <0x11000000 0x1000>; 197 reg = <0x03860000 0x1000>; 199 interrupts = <10 0>; 204 reg = <0x106E0000 0x1000>; [all …]
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D | exynos5250.dtsi | 51 #size-cells = <0>; 64 cpu0: cpu@0 { 67 reg = <0>; 180 reg = <0x02020000 0x30000>; 183 ranges = <0 0x02020000 0x30000>; 185 smp-sram@0 { 187 reg = <0x0 0x1000>; 192 reg = <0x2f000 0x1000>; 198 reg = <0x10044000 0x20>; 199 #power-domain-cells = <0>; [all …]
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D | exynos5420.dtsi | 162 reg = <0x10d20000 0x1000>; 163 ranges = <0x0 0x10d20000 0x6000>; 168 reg = <0x4000 0x1000>; 173 reg = <0x5000 0x1000>; 179 reg = <0x10010000 0x30000>; 185 reg = <0x03810000 0x0C>; 195 reg = <0x11000000 0x10000>; 208 #size-cells = <0>; 209 reg = <0x12200000 0x2000>; 212 fifo-depth = <0x40>; [all …]
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/Linux-v6.1/drivers/gpu/drm/sun4i/ |
D | sun8i_vi_scaler.c | 15 0x40000000, 0x40fe0000, 0x3ffd0100, 0x3efc0100, 16 0x3efb0100, 0x3dfa0200, 0x3cf90200, 0x3bf80200, 17 0x39f70200, 0x37f70200, 0x35f70200, 0x33f70200, 18 0x31f70200, 0x2ef70200, 0x2cf70200, 0x2af70200, 19 0x27f70200, 0x24f80100, 0x22f80100, 0x1ef90100, 20 0x1cf90100, 0x19fa0100, 0x17fa0100, 0x14fb0100, 21 0x11fc0000, 0x0ffc0000, 0x0cfd0000, 0x0afd0000, 22 0x08fe0000, 0x05ff0000, 0x03ff0000, 0x02000000, 24 0x3806fc02, 0x3805fc02, 0x3803fd01, 0x3801fe01, 25 0x3700fe01, 0x35ffff01, 0x35fdff01, 0x34fc0001, [all …]
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/Linux-v6.1/arch/arm64/boot/dts/exynos/ |
D | exynos7.dtsi | 45 #clock-cells = <0>; 50 #size-cells = <0>; 52 cpu_atlas0: cpu@0 { 55 reg = <0x0>; 57 i-cache-size = <0xc000>; 60 d-cache-size = <0x8000>; 69 reg = <0x1>; 71 i-cache-size = <0xc000>; 74 d-cache-size = <0x8000>; 83 reg = <0x2>; [all …]
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D | exynos850.dtsi | 52 #clock-cells = <0>; 57 #size-cells = <0>; 91 cpu0: cpu@0 { 94 reg = <0x0>; 100 reg = <0x1>; 106 reg = <0x2>; 112 reg = <0x3>; 118 reg = <0x100>; 124 reg = <0x101>; 130 reg = <0x102>; [all …]
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D | exynosautov9.dtsi | 47 #size-cells = <0>; 81 cpu0: cpu@0 { 84 reg = <0x0>; 91 reg = <0x100>; 98 reg = <0x200>; 105 reg = <0x300>; 112 reg = <0x10000>; 119 reg = <0x10100>; 126 reg = <0x10200>; 133 reg = <0x10300>; [all …]
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D | exynos5433.dtsi | 48 #clock-cells = <0>; 53 #size-cells = <0>; 91 reg = <0x100>; 97 i-cache-size = <0x8000>; 100 d-cache-size = <0x8000>; 110 reg = <0x101>; 114 i-cache-size = <0x8000>; 117 d-cache-size = <0x8000>; 127 reg = <0x102>; 131 i-cache-size = <0x8000>; [all …]
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/Linux-v6.1/arch/arm64/boot/dts/renesas/ |
D | r9a07g043.dtsi | 18 #clock-cells = <0>; 20 clock-frequency = <0>; 25 #clock-cells = <0>; 27 clock-frequency = <0>; 33 #clock-cells = <0>; 34 clock-frequency = <0>; 40 #clock-cells = <0>; 42 clock-frequency = <0>; 45 cluster0_opp: opp-table-0 { 74 #size-cells = <0>; [all …]
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D | r9a07g044.dtsi | 18 #clock-cells = <0>; 20 clock-frequency = <0>; 25 #clock-cells = <0>; 27 clock-frequency = <0>; 33 #clock-cells = <0>; 34 clock-frequency = <0>; 40 #clock-cells = <0>; 42 clock-frequency = <0>; 45 cluster0_opp: opp-table-0 { 74 #size-cells = <0>; [all …]
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D | r9a07g054.dtsi | 18 #clock-cells = <0>; 20 clock-frequency = <0>; 25 #clock-cells = <0>; 27 clock-frequency = <0>; 33 #clock-cells = <0>; 34 clock-frequency = <0>; 40 #clock-cells = <0>; 42 clock-frequency = <0>; 45 cluster0_opp: opp-table-0 { 74 #size-cells = <0>; [all …]
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/Linux-v6.1/drivers/net/ethernet/microchip/sparx5/ |
D | sparx5_main.c | 55 { TARGET_CPU, 0, 0 }, /* 0x600000000 */ 56 { TARGET_FDMA, 0x80000, 0 }, /* 0x600080000 */ 57 { TARGET_PCEP, 0x400000, 0 }, /* 0x600400000 */ 58 { TARGET_DEV2G5, 0x10004000, 1 }, /* 0x610004000 */ 59 { TARGET_DEV5G, 0x10008000, 1 }, /* 0x610008000 */ 60 { TARGET_PCS5G_BR, 0x1000c000, 1 }, /* 0x61000c000 */ 61 { TARGET_DEV2G5 + 1, 0x10010000, 1 }, /* 0x610010000 */ 62 { TARGET_DEV5G + 1, 0x10014000, 1 }, /* 0x610014000 */ 63 { TARGET_PCS5G_BR + 1, 0x10018000, 1 }, /* 0x610018000 */ 64 { TARGET_DEV2G5 + 2, 0x1001c000, 1 }, /* 0x61001c000 */ [all …]
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