Lines Matching +full:0 +full:x10060000
48 #clock-cells = <0>;
53 #size-cells = <0>;
91 reg = <0x100>;
97 i-cache-size = <0x8000>;
100 d-cache-size = <0x8000>;
110 reg = <0x101>;
114 i-cache-size = <0x8000>;
117 d-cache-size = <0x8000>;
127 reg = <0x102>;
131 i-cache-size = <0x8000>;
134 d-cache-size = <0x8000>;
144 reg = <0x103>;
148 i-cache-size = <0x8000>;
151 d-cache-size = <0x8000>;
157 cpu4: cpu@0 {
161 reg = <0x0>;
167 i-cache-size = <0xc000>;
170 d-cache-size = <0x8000>;
180 reg = <0x1>;
184 i-cache-size = <0xc000>;
187 d-cache-size = <0x8000>;
197 reg = <0x2>;
201 i-cache-size = <0xc000>;
204 d-cache-size = <0x8000>;
214 reg = <0x3>;
218 i-cache-size = <0xc000>;
221 d-cache-size = <0x8000>;
229 cache-size = <0x200000>;
236 cache-size = <0x40000>;
242 cluster_a53_opp_table: opp-table-0 {
357 cpu_off = <0x84000002>;
358 cpu_on = <0xC4000003>;
361 soc: soc@0 {
365 ranges = <0x0 0x0 0x0 0x18000000>;
369 reg = <0x10000000 0x100>;
374 reg = <0x10030000 0x1000>;
389 reg = <0x10fc0000 0x1000>;
398 reg = <0x105b0000 0x2000>;
409 reg = <0x14c80000 0x1000>;
415 reg = <0x10040000 0x1000>;
421 reg = <0x156e0000 0x1000>;
448 reg = <0x12460000 0x1000>;
462 reg = <0x13b90000 0x1000>;
488 reg = <0x114c0000 0x1000>;
497 reg = <0x13600000 0x1000>;
506 reg = <0x14800000 0x1000>;
515 reg = <0x13400000 0x1000>;
524 reg = <0x14aa0000 0x2000>;
534 reg = <0x13cf0000 0x1000>;
548 reg = <0x11900000 0x2000>;
557 reg = <0x11800000 0x2000>;
566 reg = <0x150d0000 0x1000>;
580 reg = <0x15280000 0x1000>;
590 reg = <0x14f80000 0x1000>;
600 reg = <0x146d0000 0x1000>;
614 reg = <0x120d0000 0x1000>;
630 reg = <0x145d0000 0x1000>;
652 reg = <0x11060000 0x1000>;
667 reg = <0x11140000 0x1000>;
676 reg = <0x105c4000 0x20>;
677 #power-domain-cells = <0>;
683 reg = <0x105c4020 0x20>;
684 #power-domain-cells = <0>;
691 reg = <0x105c4040 0x20>;
692 #power-domain-cells = <0>;
698 reg = <0x105c4060 0x20>;
699 #power-domain-cells = <0>;
705 reg = <0x105c4080 0x20>;
706 #power-domain-cells = <0>;
712 reg = <0x105c40a0 0x20>;
713 #power-domain-cells = <0>;
719 reg = <0x105c40c0 0x20>;
720 #power-domain-cells = <0>;
726 reg = <0x105c4120 0x20>;
727 #power-domain-cells = <0>;
733 reg = <0x105c4140 0x20>;
734 #power-domain-cells = <0>;
741 reg = <0x105c4180 0x20>;
742 #power-domain-cells = <0>;
748 reg = <0x105c41c0 0x20>;
749 #power-domain-cells = <0>;
755 reg = <0x10060000 0x200>;
760 #thermal-sensor-cells = <0>;
766 reg = <0x10068000 0x200>;
771 #thermal-sensor-cells = <0>;
777 reg = <0x10070000 0x200>;
782 #thermal-sensor-cells = <0>;
788 reg = <0x10078000 0x200>;
793 #thermal-sensor-cells = <0>;
799 reg = <0x1007c000 0x200>;
804 #thermal-sensor-cells = <0>;
811 reg = <0x101c0000 0x800>;
830 reg = <0x10480000 0x2000>;
836 reg = <0x10490000 0x2000>;
842 reg = <0x104b0000 0x2000>;
848 reg = <0x104c0000 0x2000>;
854 reg = <0x10580000 0x1a20>, <0x11090000 0x100>;
864 reg = <0x114b0000 0x1000>;
871 reg = <0x10fe0000 0x1000>;
877 reg = <0x14ca0000 0x1000>;
883 reg = <0x14cb0000 0x1000>;
889 reg = <0x15690000 0x1000>;
895 reg = <0x11090000 0x1000>;
901 reg = <0x14cd0000 0x1000>;
907 reg = <0x14cc0000 0x1100>;
913 reg = <0x14ce0000 0x1100>;
919 reg = <0x105c0000 0x5008>;
927 offset = <0x400>; /* SWRESET */
928 mask = <0x1>;
936 reg = <0x11001000 0x1000>,
937 <0x11002000 0x2000>,
938 <0x11004000 0x2000>,
939 <0x11006000 0x2000>;
940 interrupts = <GIC_PPI 9 0xf04>;
954 reg = <0x13800000 0x2104>;
983 #size-cells = <0>;
985 port@0 {
986 reg = <0>;
997 reg = <0x13880000 0x20b8>;
1027 reg = <0x13900000 0xC0>;
1044 #size-cells = <0>;
1048 #size-cells = <0>;
1050 port@0 {
1051 reg = <0>;
1061 reg = <0x13930000 0x48>;
1071 #size-cells = <0>;
1073 port@0 {
1074 reg = <0>;
1092 reg = <0x13970000 0x70000>;
1112 #sound-dai-cells = <0>;
1117 reg = <0x13af0000 0x80>;
1122 reg = <0x13b80000 0x1010>;
1127 reg = <0x120f0000 0x1020>;
1132 reg = <0x145f0000 0x1038>;
1137 reg = <0x156f0000 0x1044>;
1142 reg = <0x13c00000 0x1000>;
1157 reg = <0x13c10000 0x1000>;
1172 reg = <0x13c20000 0x1000>;
1187 reg = <0x14ac0000 0x5000>;
1238 reg = <0x15000000 0x1294>;
1239 interrupts = <0 402 IRQ_TYPE_LEVEL_HIGH>;
1250 reg = <0x15010000 0x1294>;
1251 interrupts = <0 403 IRQ_TYPE_LEVEL_HIGH>;
1262 reg = <0x15020000 0x10000>;
1275 reg = <0x152E0000 0x10000>;
1288 reg = <0x13a00000 0x1000>;
1294 #iommu-cells = <0>;
1299 reg = <0x13a10000 0x1000>;
1304 #iommu-cells = <0>;
1310 reg = <0x13a20000 0x1000>;
1315 #iommu-cells = <0>;
1321 reg = <0x13a30000 0x1000>;
1326 #iommu-cells = <0>;
1332 reg = <0x13C80000 0x1000>;
1337 #iommu-cells = <0>;
1343 reg = <0x13C90000 0x1000>;
1348 #iommu-cells = <0>;
1354 reg = <0x13CA0000 0x1000>;
1359 #iommu-cells = <0>;
1365 reg = <0x15040000 0x1000>;
1370 #iommu-cells = <0>;
1376 reg = <0x15050000 0x1000>;
1381 #iommu-cells = <0>;
1387 reg = <0x15060000 0x1000>;
1392 #iommu-cells = <0>;
1398 reg = <0x15200000 0x1000>;
1403 #iommu-cells = <0>;
1409 reg = <0x15210000 0x1000>;
1414 #iommu-cells = <0>;
1420 reg = <0x14c10000 0x100>;
1426 pinctrl-0 = <&uart0_bus>;
1432 reg = <0x14c20000 0x100>;
1438 pinctrl-0 = <&uart1_bus>;
1444 reg = <0x14c30000 0x100>;
1450 pinctrl-0 = <&uart2_bus>;
1456 reg = <0x14d20000 0x100>;
1461 #size-cells = <0>;
1466 samsung,spi-src-clk = <0>;
1468 pinctrl-0 = <&spi0_bus>;
1475 reg = <0x14d30000 0x100>;
1480 #size-cells = <0>;
1485 samsung,spi-src-clk = <0>;
1487 pinctrl-0 = <&spi1_bus>;
1494 reg = <0x14d40000 0x100>;
1499 #size-cells = <0>;
1504 samsung,spi-src-clk = <0>;
1506 pinctrl-0 = <&spi2_bus>;
1513 reg = <0x14d50000 0x100>;
1518 #size-cells = <0>;
1523 samsung,spi-src-clk = <0>;
1525 pinctrl-0 = <&spi3_bus>;
1532 reg = <0x14d00000 0x100>;
1537 #size-cells = <0>;
1542 samsung,spi-src-clk = <0>;
1544 pinctrl-0 = <&spi4_bus>;
1551 reg = <0x14d10000 0x100>;
1561 reg = <0x14d60000 0x100>;
1576 reg = <0x14dd0000 0x100>;
1582 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
1591 reg = <0x14e40000 0x1000>;
1594 #size-cells = <0>;
1596 pinctrl-0 = <&hs_i2c0_bus>;
1604 reg = <0x14e50000 0x1000>;
1607 #size-cells = <0>;
1609 pinctrl-0 = <&hs_i2c1_bus>;
1617 reg = <0x14e60000 0x1000>;
1620 #size-cells = <0>;
1622 pinctrl-0 = <&hs_i2c2_bus>;
1630 reg = <0x14e70000 0x1000>;
1633 #size-cells = <0>;
1635 pinctrl-0 = <&hs_i2c3_bus>;
1643 reg = <0x14ec0000 0x1000>;
1646 #size-cells = <0>;
1648 pinctrl-0 = <&hs_i2c4_bus>;
1656 reg = <0x14ed0000 0x1000>;
1659 #size-cells = <0>;
1661 pinctrl-0 = <&hs_i2c5_bus>;
1669 reg = <0x14ee0000 0x1000>;
1672 #size-cells = <0>;
1674 pinctrl-0 = <&hs_i2c6_bus>;
1682 reg = <0x14ef0000 0x1000>;
1685 #size-cells = <0>;
1687 pinctrl-0 = <&hs_i2c7_bus>;
1695 reg = <0x14d90000 0x1000>;
1698 #size-cells = <0>;
1700 pinctrl-0 = <&hs_i2c8_bus>;
1708 reg = <0x14da0000 0x1000>;
1711 #size-cells = <0>;
1713 pinctrl-0 = <&hs_i2c9_bus>;
1721 reg = <0x14de0000 0x1000>;
1724 #size-cells = <0>;
1726 pinctrl-0 = <&hs_i2c10_bus>;
1734 reg = <0x14df0000 0x1000>;
1737 #size-cells = <0>;
1739 pinctrl-0 = <&hs_i2c11_bus>;
1763 reg = <0x15400000 0x10000>;
1765 phys = <&usbdrd30_phy 0>, <&usbdrd30_phy 1>;
1772 reg = <0x15500000 0x100>;
1786 reg = <0x15580000 0x100>;
1816 reg = <0x15a00000 0x10000>;
1818 phys = <&usbhost30_phy 0>, <&usbhost30_phy 1>;
1827 #size-cells = <0>;
1828 reg = <0x15540000 0x2000>;
1832 fifo-depth = <0x40>;
1840 #size-cells = <0>;
1841 reg = <0x15550000 0x2000>;
1845 fifo-depth = <0x40>;
1853 #size-cells = <0>;
1854 reg = <0x15560000 0x2000>;
1858 fifo-depth = <0x40>;
1864 reg = <0x15610000 0x1000>;
1873 reg = <0x15600000 0x1000>;
1882 reg = <0x11400000 0x100>, <0x11500000 0x08>;
1892 reg = <0x11420000 0x1000>;
1902 reg = <0x11440000 0x100>;
1903 dmas = <&adma 0>, <&adma 2>;
1907 #size-cells = <0>;
1914 pinctrl-0 = <&i2s0_bus>;
1922 reg = <0x11460000 0x100>;
1928 pinctrl-0 = <&uart_aud_bus>;
1936 reg = <0x15680000 0x1000>;
1939 #phy-cells = <0>;
1945 reg = <0x15700000 0x1000>, <0x156b0000 0x1000>,
1946 <0x0c000000 0x1000>;
1958 bus-range = <0x00 0xff>;
1960 ranges = <0x81000000 0 0 0x0c001000 0 0x00010000>,
1961 <0x82000000 0 0x0c011000 0x0c011000 0 0x03feefff>;