Searched full:architecture (Results 1 – 25 of 197) sorted by relevance
12345678
| /Kernel-v11.1.0/portable/GCC/ARM_AARCH64/ |
| D | README.md | 1 # Armv8-A architecture support
3 The Armv8-A architecture introduces the ability to use 64-bit and 32-bit
10 backwards compatibility with the Armv7-A architecture, enhancing that profile
13 [link](https://developer.arm.com/Architectures/A-Profile%20Architecture)
18 This port adds support for Armv8-A architecture AArch64 execution state.
|
| /Kernel-v11.1.0/portable/GCC/ARM_AARCH64_SRE/ |
| D | README.md | 1 # Armv8-A architecture support
3 The Armv8-A architecture introduces the ability to use 64-bit and 32-bit
10 backwards compatibility with the Armv7-A architecture, enhancing that profile
13 [link](https://developer.arm.com/Architectures/A-Profile%20Architecture)
18 This port adds support for Armv8-A architecture AArch64 execution state.
|
| /Kernel-v11.1.0/portable/ThirdParty/GCC/ARM_TFM/ |
| D | README.md | 4 services in Trusted Firmware M(TF-M) through Platform Security Architecture
8 The Platform Security Architecture (PSA) makes it quicker, easier and cheaper
10 …, implement, and certify. See [PSA Resource Page](https://www.arm.com/architecture/security-featur…
13 for Arm M-profile architecture. Please get the details from this [link](https://www.trustedfirmware…
|
| /Kernel-v11.1.0/portable/ |
| D | readme.txt | 15 For example, if you are interested in the [compiler] port for the [architecture]
17 FreeRTOS/Source/Portable/[compiler]/[architecture] directory. If this is the
|
| D | CMakeLists.txt | 313 # RISC-V architecture ports for GCC
331 # Renesas RX architecture ports for GCC
352 # Synopsys ARC architecture ports for GCC
537 # RISC-V architecture port for IAR Embedded Workbench for RISC-V
551 # Renesas RX architecture ports for IAR EWRX
891 # RISC-V architecture ports for GCC
907 # Renesas RX architecture ports for GCC
917 # Synopsys ARC architecture ports for GCC
996 # RISC-V architecture port for IAR Embedded Workbench for RISC-V
1008 # Renesas RX architecture ports for IAR EWRX
|
| /Kernel-v11.1.0/portable/CCS/ARM_Cortex-R4/ |
| D | portmacro.h | 62 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
70 /* Architecture specifics. */
96 /* Architecture specific optimisations. */
|
| /Kernel-v11.1.0/portable/MikroC/ARM_CM4F/ |
| D | portmacro.h | 74 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
82 /* Architecture specifics. */
95 * within the specified behaviour for the architecture. */ \
144 /* Architecture specific optimisations. */
|
| /Kernel-v11.1.0/portable/GCC/ARM_CM7/r0p1/ |
| D | portmacro.h | 69 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
77 /* Architecture specifics. */
91 * within the specified behaviour for the architecture. */ \
140 /* Architecture specific optimisations. */
|
| /Kernel-v11.1.0/portable/GCC/ARM_CM4F/ |
| D | portmacro.h | 69 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
80 /* Architecture specifics. */
94 * within the specified behaviour for the architecture. */ \
143 /* Architecture specific optimisations. */
|
| /Kernel-v11.1.0/include/ |
| D | message_buffer.h | 57 * architecture, so writing a 10 byte message to a message buffer on a 32-bit
58 * architecture will actually reduce the available space in the message buffer
110 * 32-bit architecture, so on most 32-bit architectures a 10 byte message will
186 * architecture, so on most 32-bit architecture a 10 byte message will take up
333 * on a 32-bit architecture, so on most 32-bit architecture setting
436 * on a 32-bit architecture, so on most 32-bit architecture setting
840 * architecture, so if xMessageBufferSpacesAvailable() returns 10, then the size
|
| /Kernel-v11.1.0/portable/GCC/ARM_CM3/ |
| D | portmacro.h | 69 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
77 /* Architecture specifics. */
91 * within the specified behaviour for the architecture. */ \
140 /* Architecture specific optimisations. */
|
| /Kernel-v11.1.0/portable/IAR/RISC-V/ |
| D | portmacro.h | 79 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
84 /* Architecture specifics. */
137 /* Architecture specific optimisations. */
|
| /Kernel-v11.1.0/portable/CCS/ARM_CM4F/ |
| D | portmacro.h | 69 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
77 /* Architecture specifics. */
111 /* Architecture specific optimisations. */
|
| /Kernel-v11.1.0/portable/GCC/ARM_CRx_MPU/ |
| D | portmacro_asm.h | 65 /* On the ArmV7-R Architecture the Operating mode of the Processor is set
70 …* https://developer.arm.com/documentation/ddi0406/cb/System-Level-Architecture/The-System-Level-Pr…
237 …* https://developer.arm.com/documentation/ddi0406/cb/Application-Level-Architecture/Application-Le…
240 …* https://developer.arm.com/documentation/ddi0406/cb/System-Level-Architecture/The-System-Level-Pr…
|
| /Kernel-v11.1.0/portable/CCS/ARM_CM3/ |
| D | portmacro.h | 69 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
77 /* Architecture specifics. */
117 /* Architecture specific optimisations. */
|
| /Kernel-v11.1.0/portable/GCC/RISC-V/ |
| D | portmacro.h | 77 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
82 /* Architecture specifics. */
135 /* Architecture specific optimisations. */
|
| /Kernel-v11.1.0/portable/ThirdParty/xClang/XCOREAI/ |
| D | portmacro.h | 38 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
46 /* Architecture specifics. These can be used by assembly files as well. */
105 /* Architecture specific optimisations. */
|
| /Kernel-v11.1.0/portable/IAR/ARM_CM4F/ |
| D | portmacro.h | 71 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
79 /* Architecture specifics. */
119 /* Architecture specific optimisations. */
|
| /Kernel-v11.1.0/portable/IAR/ARM_CM7/r0p1/ |
| D | portmacro.h | 71 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
79 /* Architecture specifics. */
119 /* Architecture specific optimisations. */
|
| /Kernel-v11.1.0/portable/IAR/ARM_CM3/ |
| D | portmacro.h | 72 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
80 /* Architecture specifics. */
120 /* Architecture specific optimisations. */
|
| /Kernel-v11.1.0/portable/GCC/ARM_CM3_MPU/ |
| D | portmacro.h | 69 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
152 /* Architecture specifics. */
174 * within the specified behaviour for the architecture. */ \
216 /* Architecture specific optimisations. */
|
| /Kernel-v11.1.0/portable/ThirdParty/XCC/Xtensa/ |
| D | readme_xtensa.txt | 20 The Xtensa configurable architecture supports a vast space of processor
50 - Exception Architecture 2 (XEA2). Please note that XEA1 is NOT supported.
425 The Xtensa architecture specifies two ABIs that determine how the general
427 the Xtensa windowed register file architecture, and the optional and
511 The Xtensa architecture port-specific assembly files are coded with no
535 vector locations. The Xtensa architecture supports several different
536 classes of exceptions and interrupts. Being a configurable architecture,
|
| /Kernel-v11.1.0/portable/GCC/NiosII/ |
| D | portmacro.h | 70 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
78 /* Architecture specifics. */
|
| /Kernel-v11.1.0/portable/RVDS/ARM_CM4F/ |
| D | portmacro.h | 69 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
77 /* Architecture specifics. */
94 * within the specified behaviour for the architecture. */ \
|
| /Kernel-v11.1.0/portable/RVDS/ARM_CM3/ |
| D | portmacro.h | 69 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
77 /* Architecture specifics. */
94 * within the specified behaviour for the architecture. */ \
|
12345678
