1 /*
2 * FreeRTOS Kernel V11.1.0
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28
29
30 #ifndef PORTMACRO_H
31 #define PORTMACRO_H
32
33 /* *INDENT-OFF* */
34 #ifdef __cplusplus
35 extern "C" {
36 #endif
37 /* *INDENT-ON* */
38
39 /*-----------------------------------------------------------
40 * Port specific definitions.
41 *
42 * The settings in this file configure FreeRTOS correctly for the
43 * given hardware and compiler.
44 *
45 * These settings should not be altered.
46 *-----------------------------------------------------------
47 */
48
49 /* Type definitions. */
50 #define portCHAR char
51 #define portFLOAT float
52 #define portDOUBLE double
53 #define portLONG long
54 #define portSHORT short
55 #define portSTACK_TYPE uint32_t
56 #define portBASE_TYPE long
57
58 typedef portSTACK_TYPE StackType_t;
59 typedef long BaseType_t;
60 typedef unsigned long UBaseType_t;
61
62 #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
63 typedef uint16_t TickType_t;
64 #define portMAX_DELAY ( TickType_t ) 0xffff
65 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
66 typedef uint32_t TickType_t;
67 #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
68
69 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
70 * not need to be guarded with a critical section. */
71 #define portTICK_TYPE_IS_ATOMIC 1
72 #else
73 #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
74 #endif
75 /*-----------------------------------------------------------*/
76
77 /* Architecture specifics. */
78 #define portSTACK_GROWTH ( -1 )
79 #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
80 #define portBYTE_ALIGNMENT 8
81
82 /* Constants used with memory barrier intrinsics. */
83 #define portSY_FULL_READ_WRITE ( 15 )
84
85 /*-----------------------------------------------------------*/
86
87 /* Scheduler utilities. */
88 #define portYIELD() \
89 { \
90 /* Set a PendSV to request a context switch. */ \
91 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
92 \
93 /* Barriers are normally not required but do ensure the code is completely \
94 * within the specified behaviour for the architecture. */ \
95 __dsb( portSY_FULL_READ_WRITE ); \
96 __isb( portSY_FULL_READ_WRITE ); \
97 }
98 /*-----------------------------------------------------------*/
99
100 #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
101 #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
102 #define portEND_SWITCHING_ISR( xSwitchRequired ) \
103 do \
104 { \
105 if( xSwitchRequired != pdFALSE ) \
106 { \
107 traceISR_EXIT_TO_SCHEDULER(); \
108 portYIELD(); \
109 } \
110 else \
111 { \
112 traceISR_EXIT(); \
113 } \
114 } while( 0 )
115 #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
116 /*-----------------------------------------------------------*/
117
118 /* Critical section management. */
119 extern void vPortEnterCritical( void );
120 extern void vPortExitCritical( void );
121
122 #define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()
123 #define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 )
124 #define portENTER_CRITICAL() vPortEnterCritical()
125 #define portEXIT_CRITICAL() vPortExitCritical()
126 #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()
127 #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x )
128
129 /*-----------------------------------------------------------*/
130
131 /* Tickless idle/low power functionality. */
132 #ifndef portSUPPRESS_TICKS_AND_SLEEP
133 extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
134 #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
135 #endif
136 /*-----------------------------------------------------------*/
137
138 /* Port specific optimisations. */
139 #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
140 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
141 #endif
142
143 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
144
145 /* Check the configuration. */
146 #if ( configMAX_PRIORITIES > 32 )
147 #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
148 #endif
149
150 /* Store/clear the ready priorities in a bit map. */
151 #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
152 #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
153
154 /*-----------------------------------------------------------*/
155
156 #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) )
157
158 #endif /* taskRECORD_READY_PRIORITY */
159 /*-----------------------------------------------------------*/
160
161 /* Task function macros as described on the FreeRTOS.org WEB site. These are
162 * not necessary for to use this port. They are defined so the common demo files
163 * (which build with all the ports) will build. */
164 #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
165 #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
166 /*-----------------------------------------------------------*/
167
168 #ifdef configASSERT
169 void vPortValidateInterruptPriority( void );
170 #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
171 #endif
172
173 /* portNOP() is not required by this port. */
174 #define portNOP()
175
176 #define portINLINE __inline
177
178 #ifndef portFORCE_INLINE
179 #define portFORCE_INLINE __forceinline
180 #endif
181
182 /*-----------------------------------------------------------*/
183
vPortSetBASEPRI(uint32_t ulBASEPRI)184 static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI )
185 {
186 __asm
187 {
188 /* Barrier instructions are not used as this function is only used to
189 * lower the BASEPRI value. */
190 /* *INDENT-OFF* */
191 msr basepri, ulBASEPRI
192 /* *INDENT-ON* */
193 }
194 }
195 /*-----------------------------------------------------------*/
196
vPortRaiseBASEPRI(void)197 static portFORCE_INLINE void vPortRaiseBASEPRI( void )
198 {
199 uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
200
201 __asm
202 {
203 /* Set BASEPRI to the max syscall priority to effect a critical
204 * section. */
205 /* *INDENT-OFF* */
206 msr basepri, ulNewBASEPRI
207 dsb
208 isb
209 /* *INDENT-ON* */
210 }
211 }
212 /*-----------------------------------------------------------*/
213
vPortClearBASEPRIFromISR(void)214 static portFORCE_INLINE void vPortClearBASEPRIFromISR( void )
215 {
216 __asm
217 {
218 /* Set BASEPRI to 0 so no interrupts are masked. This function is only
219 * used to lower the mask in an interrupt, so memory barriers are not
220 * used. */
221 /* *INDENT-OFF* */
222 msr basepri, # 0
223 /* *INDENT-ON* */
224 }
225 }
226 /*-----------------------------------------------------------*/
227
ulPortRaiseBASEPRI(void)228 static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void )
229 {
230 uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
231
232 __asm
233 {
234 /* Set BASEPRI to the max syscall priority to effect a critical
235 * section. */
236 /* *INDENT-OFF* */
237 mrs ulReturn, basepri
238 msr basepri, ulNewBASEPRI
239 dsb
240 isb
241 /* *INDENT-ON* */
242 }
243
244 return ulReturn;
245 }
246 /*-----------------------------------------------------------*/
247
xPortIsInsideInterrupt(void)248 static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void )
249 {
250 uint32_t ulCurrentInterrupt;
251 BaseType_t xReturn;
252
253 /* Obtain the number of the currently executing interrupt. */
254 __asm
255 {
256 /* *INDENT-OFF* */
257 mrs ulCurrentInterrupt, ipsr
258 /* *INDENT-ON* */
259 }
260
261 if( ulCurrentInterrupt == 0 )
262 {
263 xReturn = pdFALSE;
264 }
265 else
266 {
267 xReturn = pdTRUE;
268 }
269
270 return xReturn;
271 }
272
273
274 /* *INDENT-OFF* */
275 #ifdef __cplusplus
276 }
277 #endif
278 /* *INDENT-ON* */
279
280 #endif /* PORTMACRO_H */
281
