1 /*
2 * FreeRTOS Kernel V11.1.0
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28
29
30 #ifndef PORTMACRO_H
31 #define PORTMACRO_H
32
33 /* *INDENT-OFF* */
34 #ifdef __cplusplus
35 extern "C" {
36 #endif
37 /* *INDENT-ON* */
38
39 /*-----------------------------------------------------------
40 * Port specific definitions.
41 *
42 * The settings in this file configure FreeRTOS correctly for the
43 * given hardware and compiler.
44 *
45 * These settings should not be altered.
46 *-----------------------------------------------------------
47 */
48
49 /* Type definitions. */
50 #define portCHAR char
51 #define portFLOAT float
52 #define portDOUBLE double
53 #define portLONG long
54 #define portSHORT short
55 #define portSTACK_TYPE uint32_t
56 #define portBASE_TYPE long
57
58 typedef portSTACK_TYPE StackType_t;
59 typedef long BaseType_t;
60 typedef unsigned long UBaseType_t;
61
62 #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
63 typedef uint16_t TickType_t;
64 #define portMAX_DELAY ( TickType_t ) 0xffff
65 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
66 typedef uint32_t TickType_t;
67 #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
68
69 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
70 * not need to be guarded with a critical section. */
71 #define portTICK_TYPE_IS_ATOMIC 1
72 #else
73 #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
74 #endif
75 /*-----------------------------------------------------------*/
76
77 /* Architecture specifics. */
78 #define portSTACK_GROWTH ( -1 )
79 #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
80 #define portBYTE_ALIGNMENT 8
81 #define portDONT_DISCARD __attribute__( ( used ) )
82 /*-----------------------------------------------------------*/
83
84 /* Scheduler utilities. */
85 #define portYIELD() \
86 { \
87 /* Set a PendSV to request a context switch. */ \
88 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
89 \
90 /* Barriers are normally not required but do ensure the code is completely \
91 * within the specified behaviour for the architecture. */ \
92 __asm volatile ( "dsb" ::: "memory" ); \
93 __asm volatile ( "isb" ); \
94 }
95
96 #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
97 #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
98 #define portEND_SWITCHING_ISR( xSwitchRequired ) \
99 do \
100 { \
101 if( xSwitchRequired != pdFALSE ) \
102 { \
103 traceISR_EXIT_TO_SCHEDULER(); \
104 portYIELD(); \
105 } \
106 else \
107 { \
108 traceISR_EXIT(); \
109 } \
110 } while( 0 )
111 #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
112 /*-----------------------------------------------------------*/
113
114 /* Critical section management. */
115 extern void vPortEnterCritical( void );
116 extern void vPortExitCritical( void );
117 #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()
118 #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x )
119 #define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()
120 #define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 )
121 #define portENTER_CRITICAL() vPortEnterCritical()
122 #define portEXIT_CRITICAL() vPortExitCritical()
123
124 /*-----------------------------------------------------------*/
125
126 /* Task function macros as described on the FreeRTOS.org WEB site. These are
127 * not necessary for to use this port. They are defined so the common demo files
128 * (which build with all the ports) will build. */
129 #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
130 #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
131 /*-----------------------------------------------------------*/
132
133 /* Tickless idle/low power functionality. */
134 #ifndef portSUPPRESS_TICKS_AND_SLEEP
135 extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
136 #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
137 #endif
138 /*-----------------------------------------------------------*/
139
140 /* Architecture specific optimisations. */
141 #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
142 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
143 #endif
144
145 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
146
147 /* Generic helper function. */
ucPortCountLeadingZeros(uint32_t ulBitmap)148 __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
149 {
150 uint8_t ucReturn;
151
152 __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
153
154 return ucReturn;
155 }
156
157 /* Check the configuration. */
158 #if ( configMAX_PRIORITIES > 32 )
159 #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
160 #endif
161
162 /* Store/clear the ready priorities in a bit map. */
163 #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
164 #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
165
166 /*-----------------------------------------------------------*/
167
168 #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
169
170 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
171
172 /*-----------------------------------------------------------*/
173
174 #ifdef configASSERT
175 void vPortValidateInterruptPriority( void );
176 #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
177 #endif
178
179 /* portNOP() is not required by this port. */
180 #define portNOP()
181
182 #define portINLINE __inline
183
184 #ifndef portFORCE_INLINE
185 #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
186 #endif
187
xPortIsInsideInterrupt(void)188 portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
189 {
190 uint32_t ulCurrentInterrupt;
191 BaseType_t xReturn;
192
193 /* Obtain the number of the currently executing interrupt. */
194 __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
195
196 if( ulCurrentInterrupt == 0 )
197 {
198 xReturn = pdFALSE;
199 }
200 else
201 {
202 xReturn = pdTRUE;
203 }
204
205 return xReturn;
206 }
207
208 /*-----------------------------------------------------------*/
209
vPortRaiseBASEPRI(void)210 portFORCE_INLINE static void vPortRaiseBASEPRI( void )
211 {
212 uint32_t ulNewBASEPRI;
213
214 __asm volatile
215 (
216 " mov %0, %1 \n" \
217 " cpsid i \n" \
218 " msr basepri, %0 \n" \
219 " isb \n" \
220 " dsb \n" \
221 " cpsie i \n" \
222 : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
223 );
224 }
225
226 /*-----------------------------------------------------------*/
227
ulPortRaiseBASEPRI(void)228 portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
229 {
230 uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
231
232 __asm volatile
233 (
234 " mrs %0, basepri \n" \
235 " mov %1, %2 \n" \
236 " cpsid i \n" \
237 " msr basepri, %1 \n" \
238 " isb \n" \
239 " dsb \n" \
240 " cpsie i \n" \
241 : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
242 );
243
244 /* This return will not be reached but is necessary to prevent compiler
245 * warnings. */
246 return ulOriginalBASEPRI;
247 }
248 /*-----------------------------------------------------------*/
249
vPortSetBASEPRI(uint32_t ulNewMaskValue)250 portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
251 {
252 __asm volatile
253 (
254 " msr basepri, %0 " ::"r" ( ulNewMaskValue ) : "memory"
255 );
256 }
257 /*-----------------------------------------------------------*/
258
259 #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
260
261 /* *INDENT-OFF* */
262 #ifdef __cplusplus
263 }
264 #endif
265 /* *INDENT-ON* */
266
267 #endif /* PORTMACRO_H */
268
