| /Zephyr-latest/drivers/mdio/ |
| D | Kconfig | 27 source "drivers/mdio/Kconfig.esp32"
28 source "drivers/mdio/Kconfig.sam"
29 source "drivers/mdio/Kconfig.nxp_imx_netc"
30 source "drivers/mdio/Kconfig.nxp_s32_netc"
31 source "drivers/mdio/Kconfig.nxp_s32_gmac"
32 source "drivers/mdio/Kconfig.adin2111"
33 source "drivers/mdio/Kconfig.gpio"
34 source "drivers/mdio/Kconfig.litex"
35 source "drivers/mdio/Kconfig.nxp_enet"
36 source "drivers/mdio/Kconfig.stm32_hal"
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| D | mdio_nxp_enet_qos.c | 47 static int do_transaction(struct mdio_transaction *mdio) in do_transaction() argument
49 enet_qos_t *base = mdio->base; in do_transaction()
53 k_mutex_lock(mdio->mdio_bus_mutex, K_FOREVER); in do_transaction()
55 if (mdio->op == MDIO_OP_C22_WRITE) { in do_transaction()
58 ENET_QOS_REG_PREP(MAC_MDIO_DATA, GD, mdio->write_data); in do_transaction()
60 } else if (mdio->op == MDIO_OP_C22_READ) { in do_transaction()
72 ENET_QOS_REG_PREP(MAC_MDIO_ADDRESS, PA, mdio->portaddr) | in do_transaction()
74 ENET_QOS_REG_PREP(MAC_MDIO_ADDRESS, RDA, mdio->regaddr); in do_transaction()
95 if (mdio->op == MDIO_OP_C22_READ) { in do_transaction()
96 uint32_t val = mdio->base->MAC_MDIO_DATA; in do_transaction()
[all …]
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| D | mdio_esp32.c | 103 DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_NODELABEL(mdio))); in mdio_esp32_initialize()
105 (clock_control_subsys_t)DT_CLOCKS_CELL(DT_NODELABEL(mdio), offset); in mdio_esp32_initialize()
125 static DEVICE_API(mdio, mdio_esp32_driver_api) = {
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| D | Kconfig.dwcxgmac | 5 bool "synopsys mdio driver"
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| /Zephyr-latest/drivers/ethernet/phy/ |
| D | phy_dm8806.c | 24 const struct device *mdio; member
69 mdio_read(cfg->mdio, INT_STAT_PHY_ADDR, INT_STAT_REG_ADDR, &data); in phy_dm8806_thread_cb()
71 mdio_write(cfg->mdio, INT_STAT_PHY_ADDR, INT_STAT_REG_ADDR, data); in phy_dm8806_thread_cb()
128 res = mdio_read(cfg->mdio, INT_MASK_CTRL_PHY_ADDR, INT_MASK_CTRL_REG_ADDR, &data); in phy_dm8806_init_interrupt()
134 res = mdio_write(cfg->mdio, INT_MASK_CTRL_PHY_ADDR, INT_MASK_CTRL_REG_ADDR, data); in phy_dm8806_init_interrupt()
143 res = mdio_read(cfg->mdio, WOLL_CTRL_REG_PHY_ADDR, WOLL_CTRL_REG_REG_ADDR, &data); in phy_dm8806_init_interrupt()
149 res = mdio_write(cfg->mdio, WOLL_CTRL_REG_PHY_ADDR, WOLL_CTRL_REG_REG_ADDR, data); in phy_dm8806_init_interrupt()
210 ret = mdio_read(cfg->mdio, PHY_ADDRESS_18H, PORT5_MAC_CONTROL, &val); in phy_dm8806_init()
220 ret = mdio_write(cfg->mdio, PHY_ADDRESS_18H, PORT5_MAC_CONTROL, val); in phy_dm8806_init()
226 ret = mdio_read(cfg->mdio, PHY_ADDRESS_18H, IRQ_LED_CONTROL, &val); in phy_dm8806_init()
[all …]
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| D | phy_adin2111.c | 92 const struct device *mdio; member
114 return mdio_read(cfg->mdio, cfg->phy_addr, reg, val); in phy_adin2111_c22_read()
122 return mdio_write(cfg->mdio, cfg->phy_addr, reg, val); in phy_adin2111_c22_write()
131 rval = mdio_write(cfg->mdio, cfg->phy_addr, ADIN1100_MMD_ACCESS_CNTRL, devad); in phy_adin2111_c45_setup_dev_reg()
135 rval = mdio_write(cfg->mdio, cfg->phy_addr, ADIN1100_MMD_ACCESS, reg); in phy_adin2111_c45_setup_dev_reg()
140 return mdio_write(cfg->mdio, cfg->phy_addr, ADIN1100_MMD_ACCESS_CNTRL, devad | BIT(14)); in phy_adin2111_c45_setup_dev_reg()
156 return mdio_read(cfg->mdio, cfg->phy_addr, ADIN1100_MMD_ACCESS, val); in phy_adin2111_c45_read()
159 return mdio_read_c45(cfg->mdio, cfg->phy_addr, devad, reg, val); in phy_adin2111_c45_read()
175 return mdio_write(cfg->mdio, cfg->phy_addr, ADIN1100_MMD_ACCESS, val); in phy_adin2111_c45_write()
178 return mdio_write_c45(cfg->mdio, cfg->phy_addr, devad, reg, val); in phy_adin2111_c45_write()
[all …]
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| D | phy_tja1103.c | 58 const struct device *mdio; member
83 return mdio_read(cfg->mdio, cfg->phy_addr, reg, val); in phy_tja1103_c22_read()
90 return mdio_write(cfg->mdio, cfg->phy_addr, reg, val); in phy_tja1103_c22_write()
98 return mdio_write_c45(cfg->mdio, cfg->phy_addr, devad, reg, val); in phy_tja1103_c45_write()
106 return mdio_read_c45(cfg->mdio, cfg->phy_addr, devad, reg, val); in phy_tja1103_c45_read()
114 mdio_bus_enable(cfg->mdio); in phy_tja1103_reg_read()
118 mdio_bus_disable(cfg->mdio); in phy_tja1103_reg_read()
128 mdio_bus_enable(cfg->mdio); in phy_tja1103_reg_write()
132 mdio_bus_disable(cfg->mdio); in phy_tja1103_reg_write()
449 .mdio = DEVICE_DT_GET(DT_INST_BUS(n)), \
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| D | phy_mii.c | 26 const struct device * const mdio; member
53 if (cfg->mdio == NULL) { in phy_mii_reg_read()
56 return mdio_read(cfg->mdio, cfg->phy_addr, reg_addr, value); in phy_mii_reg_read()
65 if (cfg->mdio == NULL) { in phy_mii_reg_write()
68 return mdio_write(cfg->mdio, cfg->phy_addr, reg_addr, value); in phy_mii_reg_write()
453 mdio_bus_enable(cfg->mdio); in phy_mii_initialize()
505 .mdio = UTIL_AND(UTIL_NOT(IS_FIXED_LINK(n)), \
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| /Zephyr-latest/tests/drivers/build_all/mdio/ |
| D | app.overlay | 26 test_mdio0: mdio@11112222 {
27 compatible = "zephyr,mdio-gpio";
30 mdio-gpios = <&test_gpio 0 0>;
36 test_mdio1: mdio@33334444 {
37 compatible = "zephyr,mdio-gpio";
40 mdio-gpios = <&test_gpio 0 0>;
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| /Zephyr-latest/dts/arm/atmel/ |
| D | same5x.dtsi | 23 mdio: mdio@42000800 { label
24 compatible = "atmel,sam-mdio";
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| /Zephyr-latest/tests/drivers/build_all/ethernet/ |
| D | app.overlay | 22 test_mdio: mdio {
23 compatible = "zephyr,mdio-gpio";
25 mdio-gpios = <&test_gpio 0 0>;
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| D | spi_devices.overlay | 79 mdio {
80 compatible = "adi,adin2111-mdio";
107 mdio {
108 compatible = "adi,adin2111-mdio";
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| /Zephyr-latest/samples/net/zperf/boards/ |
| D | fvp_baser_aemv8r.overlay | 9 &mdio {
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| D | fvp_base_revc_2xaemv8a.overlay | 9 &mdio {
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| /Zephyr-latest/samples/net/dhcpv4_client/boards/ |
| D | fvp_base_revc_2xaemv8a.overlay | 9 &mdio {
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| D | fvp_baser_aemv8r.overlay | 9 &mdio {
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| /Zephyr-latest/tests/boards/espressif/ethernet/boards/ |
| D | esp32_ethernet_kit_procpu.overlay | 15 &mdio {
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| /Zephyr-latest/dts/arm64/fvp/ |
| D | fvp-aemv8r.dtsi | 118 mdio: mdio { label
119 compatible = "smsc,lan91c111-mdio";
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| /Zephyr-latest/samples/boards/espressif/ethernet/boards/ |
| D | esp32_ethernet_kit_procpu.overlay | 15 &mdio {
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| /Zephyr-latest/samples/net/secure_mqtt_sensor_actuator/boards/ |
| D | adi_eval_adin1110ebz.overlay | 8 mdio {
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| /Zephyr-latest/boards/atmel/sam/sam_e70_xplained/ |
| D | pre_dt_board.cmake | 5 # - /soc/ethernet@40050000 & /soc/mdio@40050000
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| /Zephyr-latest/boards/atmel/sam/sam_v71_xult/ |
| D | pre_dt_board.cmake | 5 # - /soc/ethernet@40050000 & /soc/mdio@40050000
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| /Zephyr-latest/boards/arm/fvp_base_revc_2xaemv8a/ |
| D | fvp_base_revc_2xaemv8a.dts | 146 mdio: mdio { label
147 compatible = "smsc,lan91c111-mdio";
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| /Zephyr-latest/dts/arm64/intel/ |
| D | intel_socfpga_agilex5.dtsi | 293 mdio0: mdio@10810000 {
298 compatible = "snps,dwcxgmac-mdio";
317 mdio1: mdio@10820000 {
322 compatible = "snps,dwcxgmac-mdio";
341 mdio2: mdio@10830000 {
346 compatible = "snps,dwcxgmac-mdio";
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| /Zephyr-latest/drivers/ethernet/ |
| D | eth_gecko.c | 455 for (idx = 0; idx < ARRAY_SIZE(cfg->pin_list->mdio); idx++) { in eth_init_pins()
456 GPIO_PinModeSet(cfg->pin_list->mdio[idx].port, cfg->pin_list->mdio[idx].pin, in eth_init_pins()
457 cfg->pin_list->mdio[idx].mode, cfg->pin_list->mdio[idx].out); in eth_init_pins()
653 .mdio = PIN_LIST_PHY,
661 .pin_list_size = ARRAY_SIZE(pins_eth0.mdio) +
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