Lines Matching refs:mdio
92 const struct device *mdio; member
114 return mdio_read(cfg->mdio, cfg->phy_addr, reg, val); in phy_adin2111_c22_read()
122 return mdio_write(cfg->mdio, cfg->phy_addr, reg, val); in phy_adin2111_c22_write()
131 rval = mdio_write(cfg->mdio, cfg->phy_addr, ADIN1100_MMD_ACCESS_CNTRL, devad); in phy_adin2111_c45_setup_dev_reg()
135 rval = mdio_write(cfg->mdio, cfg->phy_addr, ADIN1100_MMD_ACCESS, reg); in phy_adin2111_c45_setup_dev_reg()
140 return mdio_write(cfg->mdio, cfg->phy_addr, ADIN1100_MMD_ACCESS_CNTRL, devad | BIT(14)); in phy_adin2111_c45_setup_dev_reg()
156 return mdio_read(cfg->mdio, cfg->phy_addr, ADIN1100_MMD_ACCESS, val); in phy_adin2111_c45_read()
159 return mdio_read_c45(cfg->mdio, cfg->phy_addr, devad, reg, val); in phy_adin2111_c45_read()
175 return mdio_write(cfg->mdio, cfg->phy_addr, ADIN1100_MMD_ACCESS, val); in phy_adin2111_c45_write()
178 return mdio_write_c45(cfg->mdio, cfg->phy_addr, devad, reg, val); in phy_adin2111_c45_write()
187 mdio_bus_enable(cfg->mdio); in phy_adin2111_reg_read()
191 mdio_bus_disable(cfg->mdio); in phy_adin2111_reg_read()
202 mdio_bus_enable(cfg->mdio); in phy_adin2111_reg_write()
206 mdio_bus_disable(cfg->mdio); in phy_adin2111_reg_write()
635 .mdio = DEVICE_DT_GET(DT_INST_BUS(n)), \