Searched refs:irq_mask (Results 1 – 9 of 9) sorted by relevance
33 uint32_t irq_mask; in arch_irq_enable() local37 irq_mask = ST0_IP0 << irq; in arch_irq_enable()38 mips_cp0_status_int_mask |= irq_mask; in arch_irq_enable()39 write_c0_status(read_c0_status() | irq_mask); in arch_irq_enable()47 uint32_t irq_mask; in arch_irq_disable() local51 irq_mask = ST0_IP0 << irq; in arch_irq_disable()52 mips_cp0_status_int_mask &= ~irq_mask; in arch_irq_disable()53 write_c0_status(read_c0_status() & ~irq_mask); in arch_irq_disable()
33 static uint64_t irq_mask; variable50 irq_mask = 0U; /* Let's assume all interrupts are disable at boot */ in hw_irq_ctrl_init()142 irq_premask &= ~irq_mask; in hw_irq_ctrl_clear_all_enabled_irqs()153 irq_mask &= ~((uint64_t)1<<irq); in hw_irq_ctrl_disable_irq()158 return (irq_mask & ((uint64_t)1 << irq))?1:0; in hw_irq_ctrl_is_irq_enabled()163 return irq_mask; in hw_irq_ctrl_get_irq_mask()183 irq_mask |= ((uint64_t)1<<irq); in hw_irq_ctrl_enable_irq()195 if (irq_mask & (1 << irq)) { in hw_irq_ctrl_irq_raise_prefix()
32 static uint64_t irq_mask; variable49 irq_mask = 0U; /* Let's assume all interrupts are disable at boot */ in hw_irq_ctrl_init()143 irq_premask &= ~irq_mask; in hw_irq_ctrl_clear_all_enabled_irqs()154 irq_mask &= ~((uint64_t)1<<irq); in hw_irq_ctrl_disable_irq()159 return (irq_mask & ((uint64_t)1 << irq))?1:0; in hw_irq_ctrl_is_irq_enabled()167 return irq_mask; in hw_irq_ctrl_get_irq_mask()193 irq_mask |= ((uint64_t)1<<irq); in hw_irq_ctrl_enable_irq()204 if (irq_mask & ((uint64_t)1 << irq)) { in hw_irq_ctrl_irq_raise_prefix()
11 uint32_t irq_mask; member21 return (*cfg->enable_reg | (BIT(irq) & cfg->irq_mask)) != 0; in intc_mtk_adsp_get_enable()30 if ((BIT(irq) & cfg->irq_mask) != 0) { in intc_mtk_adsp_set_enable()42 uint32_t irqs = *cfg->status_reg & cfg->irq_mask; in intc_isr()76 .irq_mask = DT_INST_PROP(N, mask), \
57 uint64_t irq_mask; in wkpu_nxp_s32_interrupt_handler() local61 irq_mask = LSB_GET(pending); in wkpu_nxp_s32_interrupt_handler()62 irq = u64_count_trailing_zeros(irq_mask); in wkpu_nxp_s32_interrupt_handler()65 REG_WRITE(WKPU_WISR(irq / 32U), REG_READ(WKPU_WISR(irq / 32U)) | irq_mask); in wkpu_nxp_s32_interrupt_handler()71 pending ^= irq_mask; in wkpu_nxp_s32_interrupt_handler()
16 #define IRQ_MASK DT_INST_REG_ADDR_BY_NAME(0, irq_mask)
203 unsigned int irq_mask; in soc_adsp_halt_cpu() local209 irq_mask = CAVS_L2_IDC; in soc_adsp_halt_cpu()217 irq_mask |= CAVS_L2_DWCT0; in soc_adsp_halt_cpu()220 CAVS_INTCTRL[id].l2.set = irq_mask; in soc_adsp_halt_cpu()
166 uint8_t irq_mask = 0; in gpio_b91_irq_set() local174 irq_mask = FLD_GPIO_IRQ_MASK_GPIO; in gpio_b91_irq_set()177 irq_mask = FLD_GPIO_IRQ_MASK_GPIO2RISC0; in gpio_b91_irq_set()180 irq_mask = FLD_GPIO_IRQ_MASK_GPIO2RISC1; in gpio_b91_irq_set()210 BM_SET(reg_gpio_irq_risc_mask, irq_mask); in gpio_b91_irq_set()
52 reg-names = "irq_mask", "irq_pending";
