1 /*
2 * Copyright (c) 2018 - 2021 Antmicro <www.antmicro.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT litex_vexriscv_intc0
8
9 #include <zephyr/kernel.h>
10 #include <zephyr/arch/cpu.h>
11 #include <zephyr/irq.h>
12 #include <zephyr/device.h>
13 #include <zephyr/types.h>
14 #include <zephyr/arch/riscv/irq.h>
15
16 #define IRQ_MASK DT_INST_REG_ADDR_BY_NAME(0, irq_mask)
17 #define IRQ_PENDING DT_INST_REG_ADDR_BY_NAME(0, irq_pending)
18
vexriscv_litex_irq_setmask(uint32_t mask)19 static inline void vexriscv_litex_irq_setmask(uint32_t mask)
20 {
21 __asm__ volatile ("csrw %0, %1" :: "i"(IRQ_MASK), "r"(mask));
22 }
23
vexriscv_litex_irq_getmask(void)24 static inline uint32_t vexriscv_litex_irq_getmask(void)
25 {
26 uint32_t mask;
27
28 __asm__ volatile ("csrr %0, %1" : "=r"(mask) : "i"(IRQ_MASK));
29 return mask;
30 }
31
vexriscv_litex_irq_pending(void)32 static inline uint32_t vexriscv_litex_irq_pending(void)
33 {
34 uint32_t pending;
35
36 __asm__ volatile ("csrr %0, %1" : "=r"(pending) : "i"(IRQ_PENDING));
37 return pending;
38 }
39
vexriscv_litex_irq_setie(uint32_t ie)40 static inline void vexriscv_litex_irq_setie(uint32_t ie)
41 {
42 if (ie) {
43 __asm__ volatile ("csrrs x0, mstatus, %0"
44 :: "r"(MSTATUS_IEN));
45 } else {
46 __asm__ volatile ("csrrc x0, mstatus, %0"
47 :: "r"(MSTATUS_IEN));
48 }
49 }
50
51 #define LITEX_IRQ_ADD_HELPER(n) \
52 if (irqs & (1 << DT_IRQN(n))) { \
53 ite = &_sw_isr_table[DT_IRQN(n)]; \
54 ite->isr(ite->arg); \
55 }
56
57 #define LITEX_IRQ_ADD(n) IF_ENABLED(DT_IRQ_HAS_IDX(n, 0), (LITEX_IRQ_ADD_HELPER(n)))
58
vexriscv_litex_irq_handler(const void * device)59 static void vexriscv_litex_irq_handler(const void *device)
60 {
61 struct _isr_table_entry *ite;
62 uint32_t pending, mask, irqs;
63
64 pending = vexriscv_litex_irq_pending();
65 mask = vexriscv_litex_irq_getmask();
66 irqs = pending & mask;
67
68 DT_FOREACH_STATUS_OKAY_NODE(LITEX_IRQ_ADD);
69 }
70
arch_irq_enable(unsigned int irq)71 void arch_irq_enable(unsigned int irq)
72 {
73 vexriscv_litex_irq_setmask(vexriscv_litex_irq_getmask() | (1 << irq));
74 }
75
arch_irq_disable(unsigned int irq)76 void arch_irq_disable(unsigned int irq)
77 {
78 vexriscv_litex_irq_setmask(vexriscv_litex_irq_getmask() & ~(1 << irq));
79 }
80
arch_irq_is_enabled(unsigned int irq)81 int arch_irq_is_enabled(unsigned int irq)
82 {
83 return vexriscv_litex_irq_getmask() & (1 << irq);
84 }
85
vexriscv_litex_irq_init(const struct device * dev)86 static int vexriscv_litex_irq_init(const struct device *dev)
87 {
88 __asm__ volatile ("csrrs x0, mie, %0"
89 :: "r"(1 << RISCV_IRQ_MEXT));
90 vexriscv_litex_irq_setie(1);
91 IRQ_CONNECT(RISCV_IRQ_MEXT, 0, vexriscv_litex_irq_handler,
92 NULL, 0);
93
94 return 0;
95 }
96
97 DEVICE_DT_INST_DEFINE(0, vexriscv_litex_irq_init, NULL, NULL, NULL,
98 PRE_KERNEL_1, CONFIG_INTC_INIT_PRIORITY, NULL);
99
