Searched refs:design (Results 1 – 25 of 208) sorted by relevance
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| /Zephyr-latest/boards/intel/niosv_g/doc/ |
| D | index.rst | 17 Nios® V/g hello world example design system
20 Prebuilt Nios® V/g hello world example design system is available in Intel FPGA Design store.
21 …tel.com/content/www/us/en/support/programmable/support-resources/design-examples/design-store.html…
23 For example, Arria10 Nios® V/g processor example design system prebuilt files can be downloaded fro…
24 - https://www.intel.com/content/www/us/en/design-example/776196/intel-arria-10-fpga-hello-world-des…
26 ready_to_test/top.sof file is the prebuilt SRAM Object File for hello world example design system a…
28 Create Nios® V/g processor example design system in FPGA
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| /Zephyr-latest/boards/intel/niosv_m/doc/ |
| D | index.rst | 17 Nios® V/m hello world example design system
20 Prebuilt Nios® V/m hello world example design system is available in Intel FPGA Design store.
21 …tel.com/content/www/us/en/support/programmable/support-resources/design-examples/design-store.html…
23 For example, Arria10 Nios® V/m processor example design system prebuilt files can be downloaded fro…
24 - https://www.intel.com/content/www/us/en/design-example/763960/arria10-niosv-based-helloworld-exam…
26 ready_to_test/top.sof file is the prebuilt SRAM Object File for hello world example design system a…
28 Create Nios® V/m processor example design system in FPGA
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| /Zephyr-latest/samples/sensor/max17262/ |
| D | app.overlay | 13 design-voltage = <3600>;
16 design-cap = <17000>;
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| /Zephyr-latest/boards/digilent/arty_a7/doc/ |
| D | index.rst | 32 both the Cortex-M1 and the Cortex-M3 reference designs. The Cortex-M1 design
34 design only targets the Artix-7 based boards. Zephyr only supports the Artix-7
48 hardware features of the Cortex-M1 reference design:
69 supports the following hardware features of the Cortex-M3 reference design:
85 The Cortex-M1 reference design is configured to use the 100 MHz external
87 design is configured for 50MHz CPU system clock.
92 The reference design contains one Xilinx UART Lite. This UART is configured as
113 First, configure the FPGA with the selected reference design FPGA bitstream
115 Xilinx edition user guide (available as part of the reference design download
118 Another option for configuring the FPGA with the reference design bitstream is
[all …]
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| /Zephyr-latest/soc/altr/zephyr_nios2f/cpu/ |
| D | README | 1 These files are a Nios II/F CPU design provided by Altera for evaluating
2 Zephyr on Nios II. This design is intended for the Altera MAX10 10M50 Rec C
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| /Zephyr-latest/boards/shields/lcd_par_s035/doc/ |
| D | index.rst | 43 …https://www.nxp.com/design/design-center/development-boards-and-designs/general-purpose-mcus/3-5-4…
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| /Zephyr-latest/boards/nxp/common/ |
| D | board-footer.rst | 17 …https://www.nxp.com/design/design-center/software/embedded-software/mcuxpresso-for-visual-studio-c…
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| /Zephyr-latest/boards/nxp/mimxrt1180_evk/ |
| D | board.cmake | 10 # SPT can be downloaded on NXP web: https://www.nxp.com/design/design-center/software/development-s…
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| /Zephyr-latest/boards/shields/eval_adxl362_ardz/doc/ |
| D | index.rst | 46 …https://www.analog.com/media/en/reference-design-documentation/design-integration-files/eval-adxl3…
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| /Zephyr-latest/drivers/sensor/maxim/max17055/ |
| D | Kconfig | 13 time to full/empty, design voltage, temperature and remaining
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| /Zephyr-latest/doc/connectivity/usb/device/api/ |
| D | usb_dc.rst | 10 This API has some limitations by design, it does not follow :ref:`device_model_api`
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| /Zephyr-latest/boards/arduino/portenta_h7/ |
| D | arduino_portenta_h7_stm32h747xx_m7.dts | 71 /** The power supply for the Portenta H7 is based on a ST PSU reference design.
72 * The design specification from this reference design limits the maximum
74 * Refer: section 8.1 of the reference design guide.
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| /Zephyr-latest/dts/arm/microchip/mec5/ |
| D | mec5_gpspi_v2.dtsi | 8 * a completely different design. Don't ask why it was given the same name;<)
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| /Zephyr-latest/boards/ronoth/lodev/doc/ |
| D | index.rst | 8 The `full LoDev design details`_ are available on GitHub. The LoDev_ board can be purchased
16 `Board design files`_ are available on GitHub.
153 .. _full LoDev design details: https://github.com/ronoth/LoDev
155 .. _Board design files: https://github.com/ronoth/LoDev
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| /Zephyr-latest/boards/shields/rk043fn02h_ct/doc/ |
| D | index.rst | 108 …https://www.nxp.com/design/design-center/development-boards-and-designs/i-mx-evaluation-and-develo…
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| /Zephyr-latest/boards/shields/rk043fn66hs_ctg/doc/ |
| D | index.rst | 108 …https://www.nxp.com/design/design-center/development-boards-and-designs/i-mx-evaluation-and-develo…
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| /Zephyr-latest/soc/nxp/imxrt/imxrt5xx/ |
| D | Kconfig.defconfig | 16 # https://www.nxp.com/design/design-center/software/embedded-software/application-software-packs/ap…
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| /Zephyr-latest/drivers/gpio/ |
| D | Kconfig.pca95xx | 27 short-pulse interrupts due to its design.
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| /Zephyr-latest/doc/security/ |
| D | secure-coding.rst | 33 We begin with an overview of secure design as it relates to
56 adhering to a defined set of design standards. In [SALT75]_, the following,
60 - **Open design** as a design guideline incorporates the maxim that
66 - **Economy of mechanism** specifies that the underlying design of a
138 how to design secure software.
140 This requires understanding the following design principles,
143 - economy of mechanism (keep the design as simple and small as
156 - open design (security mechanisms should not depend on attacker
157 ignorance of its design, but instead on more easily protected and
169 - least common mechanism (the design should minimize the mechanisms
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| /Zephyr-latest/boards/microchip/m2gl025_miv/doc/ |
| D | index.rst | 9 `Microchip's website <https://www.microchip.com/en-us/products/fpgas-and-plds/fpga-and-soc-design-t…
32 <https://www.microchip.com/en-us/products/fpgas-and-plds/fpga-and-soc-design-tools/soc-fpga/softcon…
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| /Zephyr-latest/soc/espressif/common/ |
| D | Kconfig.spiram | 154 …The PSRAM CLOCK IO can be any unused GPIO, user can config it based on hardware design. If user use
162 The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. If user use
174 …User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram,
182 …User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram,
194 The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design.
197 IO For the reference hardware design, please refer to
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| /Zephyr-latest/doc/build/snippets/ |
| D | index.rst | 25 design.rst
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| /Zephyr-latest/boards/innblue/innblue22/ |
| D | innblue22_common.dtsi | 117 design-voltage = <3700>;
118 design-capacity = <1800>;
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| /Zephyr-latest/doc/contribute/ |
| D | proposals_and_rfcs.rst | 10 design process and produce a consensus among the project stakeholders.
33 design while it's easier to change, before the design has been fully
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| /Zephyr-latest/boards/nxp/frdm_ke17z/doc/ |
| D | index.rst | 187 …https://www.nxp.com/design/design-center/development-boards-and-designs/general-purpose-mcus/freed…
202 …https://www.nxp.com/design/design-center/software/sensor-toolbox/opensda-serial-and-debug-adapter:…
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