1# Copyright 2024 NXP 2# SPDX-License-Identifier: Apache-2.0 3 4if SOC_MIMXRT595S_CM33 5 6config FLEXSPI_CONFIG_BLOCK_OFFSET 7 default 0x400 8 9config CODE_DATA_RELOCATION_SRAM 10 default y if FLASH_MCUX_FLEXSPI_XIP 11 12config ROM_START_OFFSET 13 default 0x1200 if NXP_IMXRT_BOOT_HEADER 14 15# The PVT Sensor uses IRQ #75. For more details, see 16# https://www.nxp.com/design/design-center/software/embedded-software/application-software-packs/application-software-pack-dynamic-voltage-scaling-using-pvt-sensor:APP-SW-PACK-DVS-PVT-SENSOR 17config NUM_IRQS 18 default 76 19 20config ZTEST_NO_YIELD 21 default y if (PM && ZTEST) 22 23if MBEDTLS 24# 25# MBEDTLS CTR_DRBG code path needs extra stack space for initialization than 26# what the ztest_thread_stack defaults to. 27# 28config TEST_EXTRA_STACK_SIZE 29 default 1024 30endif # MBEDTLS 31 32if MCUX_OS_TIMER 33 34config SYS_CLOCK_HW_CYCLES_PER_SEC 35 default 1000000 36 37endif # MCUX_OS_TIMER 38 39if CORTEX_M_SYSTICK 40 41config SYS_CLOCK_HW_CYCLES_PER_SEC 42 default 250105263 43 44endif # CORTEX_M_SYSTICK 45 46if PM_DEVICE 47# Enable the MEMC FlexSPI driver when using device power 48# management so we can reconfigure the FlexSPI pins to 49# save power. The MEMC FlexSPI driver is enabled when we 50# enable the Flash subsystem, however we would like to 51# reconfigure the FlexSPI pins even when the Flash driver 52# is disabled, hence MEMC is selected when PM_DEVICE 53# is turned on. 54config MEMC 55 default y 56 select MEMC_MCUX_FLEXSPI 57 58endif 59 60endif # SOC_MIMXRT595S_CM33 61 62if SOC_MIMXRT595S_F1 63 64config SMP 65 default n 66 67config XTENSA_TIMER 68 default y 69 70config KERNEL_ENTRY 71 default "__start" 72 73config MULTI_LEVEL_INTERRUPTS 74 default n 75 76config 2ND_LEVEL_INTERRUPTS 77 default n 78 79# To prevent test uses TEST_LOGGING_MINIMAL 80config TEST_LOGGING_DEFAULTS 81 default n 82 depends on TEST 83 84config SYS_CLOCK_HW_CYCLES_PER_SEC 85 default 198000000 86 87config XTENSA_CCOUNT_HZ 88 default SYS_CLOCK_HW_CYCLES_PER_SEC 89 90config SYS_CLOCK_TICKS_PER_SEC 91 default 1000 92 93config DYNAMIC_INTERRUPTS 94 default n 95 96config CACHE 97 default n 98 99config DCACHE 100 default n 101 102config CACHE_MANAGEMENT 103 default n 104 105config LOG 106 default n 107 108endif # SOC_MIMXRT595S_F1 109
