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/trusted-firmware-a-3.7.0/include/arch/aarch32/
Del3_common_macros.S34 ldcopr r0, SCTLR
35 orr r0, r0, r1
36 stcopr r0, SCTLR
46 ldr r0, =(SCR_RESET_VAL | SCR_SIF_BIT)
47 stcopr r0, SCR
74 ldcopr r0, NSACR
75 and r0, r0, #NSACR_IMP_DEF_MASK
76 orr r0, r0, #(NSACR_RESET_VAL | NSACR_ENABLE_FP_ACCESS)
81 orr r0, r0, #NSTRCDIS_BIT
83 stcopr r0, NSACR
[all …]
/trusted-firmware-a-3.7.0/lib/cpus/aarch32/
Dcortex_a57.S19 ldcopr16 r0, r1, CORTEX_A57_ECTLR
20 bic64_imm r0, r1, CORTEX_A57_ECTLR_SMP_BIT
21 stcopr16 r0, r1, CORTEX_A57_ECTLR
31 ldcopr16 r0, r1, CORTEX_A57_ECTLR
32 orr64_imm r0, r1, CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT
33 bic64_imm r0, r1, (CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK | \
35 stcopr16 r0, r1, CORTEX_A57_ECTLR
46 mov r0, #1
47 stcopr r0, DBGOSDLR
53 mov r0, #0
[all …]
Dcortex_a17.S15 ldcopr r0, SCTLR
16 tst r0, #SCTLR_C_BIT
22 ldcopr r0, ACTLR
23 bic r0, #CORTEX_A17_ACTLR_SMP_BIT
24 stcopr r0, ACTLR
31 ldcopr r0, ACTLR
32 orr r0, #CORTEX_A17_ACTLR_SMP_BIT
33 stcopr r0, ACTLR
52 cmp r0, #ERRATA_NOT_APPLIES
54 ldcopr r0, CORTEX_A17_IMP_DEF_REG1
[all …]
Dcortex_a72.S18 ldcopr16 r0, r1, CORTEX_A72_ECTLR
19 orr64_imm r0, r1, CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT
20 bic64_imm r0, r1, (CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK | \
22 stcopr16 r0, r1, CORTEX_A72_ECTLR
32 ldcopr16 r0, r1, CORTEX_A72_CPUACTLR
33 orr64_imm r0, r1, CORTEX_A72_CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH
34 stcopr16 r0, r1, CORTEX_A72_CPUACTLR
46 ldcopr16 r0, r1, CORTEX_A72_ECTLR
47 bic64_imm r0, r1, CORTEX_A72_ECTLR_SMP_BIT
48 stcopr16 r0, r1, CORTEX_A72_ECTLR
[all …]
Dcortex_a15.S21 ldcopr r0, SCTLR
22 tst r0, #SCTLR_C_BIT
28 ldcopr r0, ACTLR
29 bic r0, #CORTEX_A15_ACTLR_SMP_BIT
30 stcopr r0, ACTLR
36 mov r0, #0
37 stcopr r0, TLBIMVA
44 ldcopr r0, ACTLR
45 orr r0, #CORTEX_A15_ACTLR_SMP_BIT
46 stcopr r0, ACTLR
[all …]
Dcortex_a53.S24 ldcopr16 r0, r1, CORTEX_A53_ECTLR
25 bic64_imm r0, r1, CORTEX_A53_ECTLR_SMP_BIT
26 stcopr16 r0, r1, CORTEX_A53_ECTLR
43 mov r0, #ERRATA_APPLIES
60 mov r0, #ERRATA_APPLIES
81 cmp r0, #ERRATA_NOT_APPLIES
83 ldcopr r0, CORTEX_A53_L2ACTLR
84 bic r0, #CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN
85 orr r0, #CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH
86 stcopr r0, CORTEX_A53_L2ACTLR
[all …]
Dcortex_a32.S20 ldcopr16 r0, r1, CORTEX_A32_CPUECTLR_EL1
21 bic r0, r0, #CORTEX_A32_CPUECTLR_SMPEN_BIT
22 stcopr16 r0, r1, CORTEX_A32_CPUECTLR_EL1
38 ldcopr16 r0, r1, CORTEX_A32_CPUECTLR_EL1
39 orr r0, r0, #CORTEX_A32_CPUECTLR_SMPEN_BIT
40 stcopr16 r0, r1, CORTEX_A32_CPUECTLR_EL1
56 ldcopr r0, SCTLR
57 tst r0, #SCTLR_C_BIT
65 mov r0, #DC_OP_CISW
87 ldcopr r0, SCTLR
[all …]
Dcortex_a9.S15 ldcopr r0, SCTLR
16 tst r0, #SCTLR_C_BIT
22 ldcopr r0, ACTLR
23 bic r0, #CORTEX_A9_ACTLR_SMP_BIT
24 stcopr r0, ACTLR
31 ldcopr r0, ACTLR
32 orr r0, #CORTEX_A9_ACTLR_SMP_BIT
33 stcopr r0, ACTLR
40 mov r0, #ERRATA_APPLIES
42 mov r0, #ERRATA_MISSING
[all …]
Dcpu_helpers.S36 cmp r0, #0
41 ldr r1, [r0, #CPU_RESET_FUNC]
66 cmp r0, r2
67 movhi r0, r2
69 push {r0, lr}
73 ldr r0, [r0, #CPU_DATA_CPU_OPS_PTR]
75 cmp r0, #0
82 ldr r1, [r0, r1]
99 mov r6, r0
100 ldr r1, [r0, #CPU_DATA_CPU_OPS_PTR]
[all …]
/trusted-firmware-a-3.7.0/plat/arm/css/common/aarch32/
Dcss_helpers.S44 ldr r0, =PLAT_ARM_TRUSTED_MAILBOX_BASE
45 ldr r0, [r0]
58 and r1, r0, #MPIDR_CPU_MASK
59 and r0, r0, #MPIDR_CLUSTER_MASK
60 eor r0, r0, #(1 << MPIDR_AFFINITY_BITS) // swap cluster order
61 add r0, r1, r0, LSR #6
76 mov r4, r0
80 cmp r0, r1
82 cmp r0, r4
83 moveq r0, #1
[all …]
/trusted-firmware-a-3.7.0/drivers/arm/pl011/aarch32/
Dpl011_console.S42 cmp r0, #0
51 ldr r3, [r0, #UARTCR]
53 str r3, [r0, #UARTCR]
58 push {r0,r3}
59 softudiv r0,r1,r2,r3
60 mov r2, r0
61 pop {r0,r3}
68 str r1, [r0, #UARTIBRD]
72 str r1, [r0, #UARTFBRD]
74 str r1, [r0, #UARTLCR_H]
[all …]
/trusted-firmware-a-3.7.0/plat/arm/board/a5ds/aarch32/
Da5ds_helpers.S27 lsl r0, r0, #A5DS_HOLD_ENTRY_SHIFT
31 str r3, [r2, r0]
36 ldr r1, [r2, r0]
39 mov_imm r0, A5DS_TRUSTED_MAILBOX_BASE
40 ldr r1, [r0]
57 mov r0, #0
70 ldcopr r0, MPIDR
72 and r0, r1
73 cmp r0, #0
74 moveq r0, #1
[all …]
/trusted-firmware-a-3.7.0/plat/qemu/common/aarch32/
Dplat_helpers.S25 ldcopr r0, MPIDR
34 and r1, r0, #MPIDR_CPU_MASK
35 and r0, r0, #MPIDR_CLUSTER_MASK
36 add r0, r1, r0, LSR #6
48 ldcopr r0, MPIDR
50 and r0, r1
51 cmp r0, #QEMU_PRIMARY_CPU
52 moveq r0, #1
53 movne r0, #0
69 lsl r0, r0, #PLAT_QEMU_HOLD_ENTRY_SHIFT
[all …]
/trusted-firmware-a-3.7.0/bl2/aarch32/
Dbl2_entrypoint.S32 mov r9, r0
41 ldr r0, =bl2_vector_table
42 stcopr r0, VBAR
49 ldcopr r0, SCTLR
50 orr r0, r0, #SCTLR_I_BIT
51 bic r0, r0, #SCTLR_DSSBS_BIT
52 stcopr r0, SCTLR
71 ldr r0, =__RW_START__
73 sub r1, r1, r0
82 ldr r0, =__BSS_START__
[all …]
/trusted-firmware-a-3.7.0/drivers/ti/uart/aarch32/
D16550_console.S42 cmp r0, #0
57 ldr r3, [r0, #UARTLCR]
59 str r3, [r0, #UARTLCR] /* enable DLL, DLLM programming */
60 str r1, [r0, #UARTDLL] /* program DLL */
61 str r2, [r0, #UARTDLLM] /* program DLLM */
64 str r3, [r0, #UARTLCR] /* disable DLL, DLLM programming */
68 str r3, [r0, #UARTLCR]
71 str r3, [r0, #UARTIER]
74 str r3, [r0, #UARTMDR1]
78 str r3, [r0, #UARTFCR]
[all …]
/trusted-firmware-a-3.7.0/bl32/sp_min/aarch32/
Dentrypoint.S69 mov r9, r0
117 mov r0, r9
134 ldr r0, =__DATA_START__
136 sub r1, r1, r0
139 ldr r0, =__BSS_START__
141 sub r1, r1, r0
165 strd r0, r1, [sp, #SMC_CTX_GPREG_R0]
166 ldcopr16 r0, r1, CNTPCT_64
168 strd r0, r1, [lr, #-8]!
170 ldrd r0, r1, [sp, #SMC_CTX_GPREG_R0]
[all …]
/trusted-firmware-a-3.7.0/plat/arm/board/fvp/aarch32/
Dfvp_helpers.S64 mov r0, #0
74 ldr r0, =PLAT_ARM_TRUSTED_MAILBOX_BASE
75 ldr r0, [r0]
76 cmp r0, #0
97 ldcopr r0, MPIDR
99 and r0, r1
100 cmp r0, #FVP_PRIMARY_CPU
101 moveq r0, #1
102 movne r0, #0
122 mov r3, r0
[all …]
/trusted-firmware-a-3.7.0/bl2u/aarch32/
Dbl2u_entrypoint.S40 ldr r0, =bl2u_vector_table
41 stcopr r0, VBAR
48 ldcopr r0, SCTLR
49 orr r0, r0, #SCTLR_I_BIT
50 bic r0, r0, #SCTLR_DSSBS_BIT
51 stcopr r0, SCTLR
70 ldr r0, =__RW_START__
72 sub r1, r1, r0
81 ldr r0, =__BSS_START__
83 sub r1, r1, r0
[all …]
/trusted-firmware-a-3.7.0/lib/extensions/amu/aarch32/
Damu_helpers.S26 mov r1, r0
37 lsl r0, r0, #3 /* each ldcopr16/bx lr sequence is 8 bytes */
38 add r1, r1, r0
41 ldcopr16 r0, r1, AMEVCNTR00 /* index 0 */
43 ldcopr16 r0, r1, AMEVCNTR01 /* index 1 */
45 ldcopr16 r0, r1, AMEVCNTR02 /* index 2 */
47 ldcopr16 r0, r1, AMEVCNTR03 /* index 3 */
61 mov r1, r0
72 lsl r0, r0, #3 /* each stcopr16/bx lr sequence is 8 bytes */
73 add r1, r1, r0
[all …]
/trusted-firmware-a-3.7.0/plat/arm/board/juno/aarch32/
Djuno_helpers.S31 cmp r0, #\_revision
54 mov r0, #(0xf << EVNTI_SHIFT)
55 orr r0, r0, #EVNTEN_BIT
56 stcopr r0, CNTKCTL
68 mov r0, #((CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
70 stcopr r0, CORTEX_A57_L2CTLR
105 mov r0, #(CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT)
106 stcopr r0, CORTEX_A57_L2CTLR
139 mov r0, #((CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
141 stcopr r0, CORTEX_A72_L2CTLR
[all …]
/trusted-firmware-a-3.7.0/drivers/st/uart/aarch32/
Dstm32_console.S46 cmp r0, #0
55 ldr r3, [r0, #USART_CR1]
66 ldr r3, [r0, #USART_CR1]
68 str r3, [r0, #USART_CR1]
71 str r3, [r0, #USART_CR1]
72 ldr r3, [r0, #USART_CR2]
74 str r3, [r0, #USART_CR2]
90 ldr r1, [r0, #USART_CR1]
92 str r1, [r0, #USART_CR1]
94 str r3, [r0, #USART_BRR]
[all …]
/trusted-firmware-a-3.7.0/plat/rockchip/common/aarch32/
Dplat_helpers.S38 ldcopr r0, MPIDR
39 and r1, r0, #MPIDR_CPU_MASK
41 and r0, r0, #PLAT_RK_MPIDR_CLUSTER_MASK
43 and r0, r0, #MPIDR_CLUSTER_MASK
45 add r0, r1, r0, LSR #PLAT_RK_CLST_TO_CPUID_SHIFT
65 ldcopr r0, MPIDR
71 and r0, r1
72 cmp r0, #PLAT_RK_PRIMARY_CPU
73 moveq r0, #1
74 movne r0, #0
[all …]
/trusted-firmware-a-3.7.0/lib/psci/aarch32/
Dpsci_helpers.S40 mov r4, r0
48 mov r0, r4
81 sub r1, r0, r1
82 mov r0, sp
89 ldcopr r0, SCTLR
90 orr r0, r0, #SCTLR_C_BIT
91 stcopr r0, SCTLR
119 mov r4, r0
121 sub r1, r0, r1
122 mov r0, sp
[all …]
/trusted-firmware-a-3.7.0/drivers/arm/css/sds/aarch32/
Dsds_helpers.S22 ldr r0, =PLAT_ARM_SDS_MEM_BASE
24 ldr r1, [r0]
35 add r0, r0, #SDS_REGION_DESC_SIZE
40 ldrh r2, [r0]
45 ldr r0, [r0,#(SDS_HEADER_SIZE + SDS_AP_CPU_INFO_PRIMARY_CPUID_OFFSET)]
54 ldr r2, [r0,#4]
59 add r0, r0, r2
62 mov r0, #0xffffffff
/trusted-firmware-a-3.7.0/common/aarch32/
Ddebug.S50 udiv r0, r4, r5 /* Get the quotient */
51 mls r4, r0, r5, r4 /* Find the remainder */
52 add r0, r0, #ASCII_OFFSET_NUM /* Convert to ascii */
76 mov r5, r0
83 cmp r0, #0
123 ldrb r0, [r4], #0x1
124 cmp r0, #0
145 lsr r0, r4, r5
146 and r0, r0, #0xf
147 cmp r0, #0xa
[all …]

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