1/* 2 * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7#include <asm_macros.S> 8#include <assert_macros.S> 9#include <common/debug.h> 10#include <cortex_a72.h> 11#include <cpu_macros.S> 12 13 /* --------------------------------------------- 14 * Disable all types of L2 prefetches. 15 * --------------------------------------------- 16 */ 17func cortex_a72_disable_l2_prefetch 18 ldcopr16 r0, r1, CORTEX_A72_ECTLR 19 orr64_imm r0, r1, CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT 20 bic64_imm r0, r1, (CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK | \ 21 CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK) 22 stcopr16 r0, r1, CORTEX_A72_ECTLR 23 isb 24 bx lr 25endfunc cortex_a72_disable_l2_prefetch 26 27 /* --------------------------------------------- 28 * Disable the load-store hardware prefetcher. 29 * --------------------------------------------- 30 */ 31func cortex_a72_disable_hw_prefetcher 32 ldcopr16 r0, r1, CORTEX_A72_CPUACTLR 33 orr64_imm r0, r1, CORTEX_A72_CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH 34 stcopr16 r0, r1, CORTEX_A72_CPUACTLR 35 isb 36 dsb ish 37 bx lr 38endfunc cortex_a72_disable_hw_prefetcher 39 40 /* --------------------------------------------- 41 * Disable intra-cluster coherency 42 * Clobbers: r0-r1 43 * --------------------------------------------- 44 */ 45func cortex_a72_disable_smp 46 ldcopr16 r0, r1, CORTEX_A72_ECTLR 47 bic64_imm r0, r1, CORTEX_A72_ECTLR_SMP_BIT 48 stcopr16 r0, r1, CORTEX_A72_ECTLR 49 bx lr 50endfunc cortex_a72_disable_smp 51 52 /* --------------------------------------------- 53 * Disable debug interfaces 54 * --------------------------------------------- 55 */ 56func cortex_a72_disable_ext_debug 57 mov r0, #1 58 stcopr r0, DBGOSDLR 59 isb 60 dsb sy 61 bx lr 62endfunc cortex_a72_disable_ext_debug 63 64 /* --------------------------------------------------- 65 * Errata Workaround for Cortex A72 Errata #859971. 66 * This applies only to revision <= r0p3 of Cortex A72. 67 * Inputs: 68 * r0: variant[4:7] and revision[0:3] of current cpu. 69 * Shall clobber: r0-r3 70 * --------------------------------------------------- 71 */ 72func errata_a72_859971_wa 73 mov r2,lr 74 bl check_errata_859971 75 mov lr, r2 76 cmp r0, #ERRATA_NOT_APPLIES 77 beq 1f 78 ldcopr16 r0, r1, CORTEX_A72_CPUACTLR 79 orr64_imm r1, r1, CORTEX_A72_CPUACTLR_DIS_INSTR_PREFETCH 80 stcopr16 r0, r1, CORTEX_A72_CPUACTLR 811: 82 bx lr 83endfunc errata_a72_859971_wa 84 85func check_errata_859971 86 mov r1, #0x03 87 b cpu_rev_var_ls 88endfunc check_errata_859971 89 90add_erratum_entry cortex_a72, ERRATUM(859971), ERRATA_A72_859971 91 92func check_errata_cve_2017_5715 93 mov r0, #ERRATA_MISSING 94 bx lr 95endfunc check_errata_cve_2017_5715 96 97add_erratum_entry cortex_a72, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 98 99func check_errata_cve_2018_3639 100#if WORKAROUND_CVE_2018_3639 101 mov r0, #ERRATA_APPLIES 102#else 103 mov r0, #ERRATA_MISSING 104#endif 105 bx lr 106endfunc check_errata_cve_2018_3639 107 108add_erratum_entry cortex_a72, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 109 110func check_errata_cve_2022_23960 111 mov r0, #ERRATA_MISSING 112 bx lr 113endfunc check_errata_cve_2022_23960 114 115add_erratum_entry cortex_a72, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 116 117 /* ------------------------------------------------- 118 * The CPU Ops reset function for Cortex-A72. 119 * ------------------------------------------------- 120 */ 121func cortex_a72_reset_func 122 mov r5, lr 123 bl cpu_get_rev_var 124 mov r4, r0 125 126#if ERRATA_A72_859971 127 mov r0, r4 128 bl errata_a72_859971_wa 129#endif 130 131#if WORKAROUND_CVE_2018_3639 132 ldcopr16 r0, r1, CORTEX_A72_CPUACTLR 133 orr64_imm r0, r1, CORTEX_A72_CPUACTLR_DIS_LOAD_PASS_STORE 134 stcopr16 r0, r1, CORTEX_A72_CPUACTLR 135 isb 136 dsb sy 137#endif 138 139 /* --------------------------------------------- 140 * Enable the SMP bit. 141 * --------------------------------------------- 142 */ 143 ldcopr16 r0, r1, CORTEX_A72_ECTLR 144 orr64_imm r0, r1, CORTEX_A72_ECTLR_SMP_BIT 145 stcopr16 r0, r1, CORTEX_A72_ECTLR 146 isb 147 bx r5 148endfunc cortex_a72_reset_func 149 150 /* ---------------------------------------------------- 151 * The CPU Ops core power down function for Cortex-A72. 152 * ---------------------------------------------------- 153 */ 154func cortex_a72_core_pwr_dwn 155 push {r12, lr} 156 157 /* Assert if cache is enabled */ 158#if ENABLE_ASSERTIONS 159 ldcopr r0, SCTLR 160 tst r0, #SCTLR_C_BIT 161 ASM_ASSERT(eq) 162#endif 163 164 /* --------------------------------------------- 165 * Disable the L2 prefetches. 166 * --------------------------------------------- 167 */ 168 bl cortex_a72_disable_l2_prefetch 169 170 /* --------------------------------------------- 171 * Disable the load-store hardware prefetcher. 172 * --------------------------------------------- 173 */ 174 bl cortex_a72_disable_hw_prefetcher 175 176 /* --------------------------------------------- 177 * Flush L1 caches. 178 * --------------------------------------------- 179 */ 180 mov r0, #DC_OP_CISW 181 bl dcsw_op_level1 182 183 /* --------------------------------------------- 184 * Come out of intra cluster coherency 185 * --------------------------------------------- 186 */ 187 bl cortex_a72_disable_smp 188 189 /* --------------------------------------------- 190 * Force the debug interfaces to be quiescent 191 * --------------------------------------------- 192 */ 193 pop {r12, lr} 194 b cortex_a72_disable_ext_debug 195endfunc cortex_a72_core_pwr_dwn 196 197 /* ------------------------------------------------------- 198 * The CPU Ops cluster power down function for Cortex-A72. 199 * ------------------------------------------------------- 200 */ 201func cortex_a72_cluster_pwr_dwn 202 push {r12, lr} 203 204 /* Assert if cache is enabled */ 205#if ENABLE_ASSERTIONS 206 ldcopr r0, SCTLR 207 tst r0, #SCTLR_C_BIT 208 ASM_ASSERT(eq) 209#endif 210 211 /* --------------------------------------------- 212 * Disable the L2 prefetches. 213 * --------------------------------------------- 214 */ 215 bl cortex_a72_disable_l2_prefetch 216 217 /* --------------------------------------------- 218 * Disable the load-store hardware prefetcher. 219 * --------------------------------------------- 220 */ 221 bl cortex_a72_disable_hw_prefetcher 222 223#if !SKIP_A72_L1_FLUSH_PWR_DWN 224 /* --------------------------------------------- 225 * Flush L1 caches. 226 * --------------------------------------------- 227 */ 228 mov r0, #DC_OP_CISW 229 bl dcsw_op_level1 230#endif 231 232 /* --------------------------------------------- 233 * Disable the optional ACP. 234 * --------------------------------------------- 235 */ 236 bl plat_disable_acp 237 238 /* ------------------------------------------------- 239 * Flush the L2 caches. 240 * ------------------------------------------------- 241 */ 242 mov r0, #DC_OP_CISW 243 bl dcsw_op_level2 244 245 /* --------------------------------------------- 246 * Come out of intra cluster coherency 247 * --------------------------------------------- 248 */ 249 bl cortex_a72_disable_smp 250 251 /* --------------------------------------------- 252 * Force the debug interfaces to be quiescent 253 * --------------------------------------------- 254 */ 255 pop {r12, lr} 256 b cortex_a72_disable_ext_debug 257endfunc cortex_a72_cluster_pwr_dwn 258 259errata_report_shim cortex_a72 260 261declare_cpu_ops cortex_a72, CORTEX_A72_MIDR, \ 262 cortex_a72_reset_func, \ 263 cortex_a72_core_pwr_dwn, \ 264 cortex_a72_cluster_pwr_dwn 265
