1/*
2 * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <common/bl_common.h>
10#include <common/runtime_svc.h>
11#include <context.h>
12#include <el3_common_macros.S>
13#include <lib/el3_runtime/cpu_data.h>
14#include <lib/pmf/aarch32/pmf_asm_macros.S>
15#include <lib/runtime_instr.h>
16#include <lib/xlat_tables/xlat_tables_defs.h>
17#include <smccc_helpers.h>
18#include <smccc_macros.S>
19
20	.globl	sp_min_vector_table
21	.globl	sp_min_entrypoint
22	.globl	sp_min_warm_entrypoint
23	.globl	sp_min_handle_smc
24	.globl	sp_min_handle_fiq
25
26#define FIXUP_SIZE	((BL32_LIMIT) - (BL32_BASE))
27
28	.macro route_fiq_to_sp_min reg
29		/* -----------------------------------------------------
30		 * FIQs are secure interrupts trapped by Monitor and non
31		 * secure is not allowed to mask the FIQs.
32		 * -----------------------------------------------------
33		 */
34		ldcopr	\reg, SCR
35		orr	\reg, \reg, #SCR_FIQ_BIT
36		bic	\reg, \reg, #SCR_FW_BIT
37		stcopr	\reg, SCR
38	.endm
39
40	.macro clrex_on_monitor_entry
41#if (ARM_ARCH_MAJOR == 7)
42	/*
43	 * ARMv7 architectures need to clear the exclusive access when
44	 * entering Monitor mode.
45	 */
46	clrex
47#endif
48	.endm
49
50vector_base sp_min_vector_table
51	b	sp_min_entrypoint
52	b	plat_panic_handler	/* Undef */
53	b	sp_min_handle_smc	/* Syscall */
54	b	report_prefetch_abort	/* Prefetch abort */
55	b	report_data_abort	/* Data abort */
56	b	plat_panic_handler	/* Reserved */
57	b	plat_panic_handler	/* IRQ */
58	b	sp_min_handle_fiq	/* FIQ */
59
60
61/*
62 * The Cold boot/Reset entrypoint for SP_MIN
63 */
64func sp_min_entrypoint
65	/* ---------------------------------------------------------------
66	 * Stash the previous bootloader arguments r0 - r3 for later use.
67	 * ---------------------------------------------------------------
68	 */
69	mov	r9, r0
70	mov	r10, r1
71	mov	r11, r2
72	mov	r12, r3
73
74#if !RESET_TO_SP_MIN
75	/* ---------------------------------------------------------------------
76	 * For !RESET_TO_SP_MIN systems, only the primary CPU ever reaches
77	 * sp_min_entrypoint() during the cold boot flow, so the cold/warm boot
78	 * and primary/secondary CPU logic should not be executed in this case.
79	 *
80	 * Also, assume that the previous bootloader has already initialised the
81	 * SCTLR, including the CPU endianness, and has initialised the memory.
82	 * ---------------------------------------------------------------------
83	 */
84	el3_entrypoint_common					\
85		_init_sctlr=0					\
86		_warm_boot_mailbox=0				\
87		_secondary_cold_boot=0				\
88		_init_memory=0					\
89		_init_c_runtime=1				\
90		_exception_vectors=sp_min_vector_table		\
91		_pie_fixup_size=FIXUP_SIZE
92#else
93	/* ---------------------------------------------------------------------
94	 * For RESET_TO_SP_MIN systems which have a programmable reset address,
95	 * sp_min_entrypoint() is executed only on the cold boot path so we can
96	 * skip the warm boot mailbox mechanism.
97	 * ---------------------------------------------------------------------
98	 */
99	el3_entrypoint_common					\
100		_init_sctlr=1					\
101		_warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS	\
102		_secondary_cold_boot=!COLD_BOOT_SINGLE_CPU	\
103		_init_memory=1					\
104		_init_c_runtime=1				\
105		_exception_vectors=sp_min_vector_table		\
106		_pie_fixup_size=FIXUP_SIZE
107#endif /* RESET_TO_SP_MIN */
108
109#if SP_MIN_WITH_SECURE_FIQ
110	route_fiq_to_sp_min r4
111#endif
112
113	/* ---------------------------------------------------------------------
114	 * Relay the previous bootloader's arguments to the platform layer
115	 * ---------------------------------------------------------------------
116	 */
117	mov	r0, r9
118	mov	r1, r10
119	mov	r2, r11
120	mov	r3, r12
121	bl	sp_min_early_platform_setup2
122	bl	sp_min_plat_arch_setup
123
124	/* Jump to the main function */
125	bl	sp_min_main
126
127	/* -------------------------------------------------------------
128	 * Clean the .data & .bss sections to main memory. This ensures
129	 * that any global data which was initialised by the primary CPU
130	 * is visible to secondary CPUs before they enable their data
131	 * caches and participate in coherency.
132	 * -------------------------------------------------------------
133	 */
134	ldr	r0, =__DATA_START__
135	ldr	r1, =__DATA_END__
136	sub	r1, r1, r0
137	bl	clean_dcache_range
138
139	ldr	r0, =__BSS_START__
140	ldr	r1, =__BSS_END__
141	sub	r1, r1, r0
142	bl	clean_dcache_range
143
144	bl	smc_get_next_ctx
145
146	/* r0 points to `smc_ctx_t` */
147	/* The PSCI cpu_context registers have been copied to `smc_ctx_t` */
148	b	sp_min_exit
149endfunc sp_min_entrypoint
150
151
152/*
153 * SMC handling function for SP_MIN.
154 */
155func sp_min_handle_smc
156	/* On SMC entry, `sp` points to `smc_ctx_t`. Save `lr`. */
157	str	lr, [sp, #SMC_CTX_LR_MON]
158
159#if ENABLE_RUNTIME_INSTRUMENTATION
160	/*
161	 * Read the timestamp value and store it on top of the C runtime stack.
162	 * The value will be saved to the per-cpu data once the C stack is
163	 * available, as a valid stack is needed to call _cpu_data()
164	 */
165	strd	r0, r1, [sp, #SMC_CTX_GPREG_R0]
166	ldcopr16 r0, r1, CNTPCT_64
167	ldr	lr, [sp, #SMC_CTX_SP_MON]
168	strd	r0, r1, [lr, #-8]!
169	str	lr, [sp, #SMC_CTX_SP_MON]
170	ldrd	r0, r1, [sp, #SMC_CTX_GPREG_R0]
171#endif
172
173	smccc_save_gp_mode_regs
174
175	clrex_on_monitor_entry
176
177	/*
178	 * `sp` still points to `smc_ctx_t`. Save it to a register
179	 * and restore the C runtime stack pointer to `sp`.
180	 */
181	mov	r2, sp				/* handle */
182	ldr	sp, [r2, #SMC_CTX_SP_MON]
183
184#if ENABLE_RUNTIME_INSTRUMENTATION
185	/* Save handle to a callee saved register */
186	mov	r6, r2
187
188	/*
189	 * Restore the timestamp value and store it in per-cpu data. The value
190	 * will be extracted from per-cpu data by the C level SMC handler and
191	 * saved to the PMF timestamp region.
192	 */
193	ldrd	r4, r5, [sp], #8
194	bl	_cpu_data
195	strd	r4, r5, [r0, #CPU_DATA_PMF_TS0_OFFSET]
196
197	/* Restore handle */
198	mov	r2, r6
199#endif
200
201	ldr	r0, [r2, #SMC_CTX_SCR]
202	and	r3, r0, #SCR_NS_BIT		/* flags */
203
204	/* Switch to Secure Mode*/
205	bic	r0, #SCR_NS_BIT
206	stcopr	r0, SCR
207	isb
208
209	ldr	r0, [r2, #SMC_CTX_GPREG_R0]	/* smc_fid */
210	/* Check whether an SMC64 is issued */
211	tst	r0, #(FUNCID_CC_MASK << FUNCID_CC_SHIFT)
212	beq	1f
213	/* SMC32 is not detected. Return error back to caller */
214	mov	r0, #SMC_UNK
215	str	r0, [r2, #SMC_CTX_GPREG_R0]
216	mov	r0, r2
217	b	sp_min_exit
2181:
219	/* SMC32 is detected */
220	mov	r1, #0				/* cookie */
221	bl	handle_runtime_svc
222
223	/* `r0` points to `smc_ctx_t` */
224	b	sp_min_exit
225endfunc sp_min_handle_smc
226
227/*
228 * Secure Interrupts handling function for SP_MIN.
229 */
230func sp_min_handle_fiq
231#if !SP_MIN_WITH_SECURE_FIQ
232	b plat_panic_handler
233#else
234	/* FIQ has a +4 offset for lr compared to preferred return address */
235	sub	lr, lr, #4
236	/* On SMC entry, `sp` points to `smc_ctx_t`. Save `lr`. */
237	str	lr, [sp, #SMC_CTX_LR_MON]
238
239	smccc_save_gp_mode_regs
240
241	clrex_on_monitor_entry
242
243	/* load run-time stack */
244	mov	r2, sp
245	ldr	sp, [r2, #SMC_CTX_SP_MON]
246
247	/* Switch to Secure Mode */
248	ldr	r0, [r2, #SMC_CTX_SCR]
249	bic	r0, #SCR_NS_BIT
250	stcopr	r0, SCR
251	isb
252
253	push	{r2, r3}
254	bl	sp_min_fiq
255	pop	{r0, r3}
256
257	b	sp_min_exit
258#endif
259endfunc sp_min_handle_fiq
260
261/*
262 * The Warm boot entrypoint for SP_MIN.
263 */
264func sp_min_warm_entrypoint
265#if ENABLE_RUNTIME_INSTRUMENTATION
266	/*
267	 * This timestamp update happens with cache off.  The next
268	 * timestamp collection will need to do cache maintenance prior
269	 * to timestamp update.
270	 */
271	pmf_calc_timestamp_addr rt_instr_svc, RT_INSTR_EXIT_HW_LOW_PWR
272	ldcopr16 r2, r3, CNTPCT_64
273	strd	r2, r3, [r0]
274#endif
275	/*
276	 * On the warm boot path, most of the EL3 initialisations performed by
277	 * 'el3_entrypoint_common' must be skipped:
278	 *
279	 *  - Only when the platform bypasses the BL1/BL32 (SP_MIN) entrypoint by
280	 *    programming the reset address do we need to initialied the SCTLR.
281	 *    In other cases, we assume this has been taken care by the
282	 *    entrypoint code.
283	 *
284	 *  - No need to determine the type of boot, we know it is a warm boot.
285	 *
286	 *  - Do not try to distinguish between primary and secondary CPUs, this
287	 *    notion only exists for a cold boot.
288	 *
289	 *  - No need to initialise the memory or the C runtime environment,
290	 *    it has been done once and for all on the cold boot path.
291	 */
292	el3_entrypoint_common					\
293		_init_sctlr=PROGRAMMABLE_RESET_ADDRESS		\
294		_warm_boot_mailbox=0				\
295		_secondary_cold_boot=0				\
296		_init_memory=0					\
297		_init_c_runtime=0				\
298		_exception_vectors=sp_min_vector_table		\
299		_pie_fixup_size=0
300
301	/*
302	 * We're about to enable MMU and participate in PSCI state coordination.
303	 *
304	 * The PSCI implementation invokes platform routines that enable CPUs to
305	 * participate in coherency. On a system where CPUs are not
306	 * cache-coherent without appropriate platform specific programming,
307	 * having caches enabled until such time might lead to coherency issues
308	 * (resulting from stale data getting speculatively fetched, among
309	 * others). Therefore we keep data caches disabled even after enabling
310	 * the MMU for such platforms.
311	 *
312	 * On systems with hardware-assisted coherency, or on single cluster
313	 * platforms, such platform specific programming is not required to
314	 * enter coherency (as CPUs already are); and there's no reason to have
315	 * caches disabled either.
316	 */
317#if HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY
318	mov	r0, #0
319#else
320	mov	r0, #DISABLE_DCACHE
321#endif
322	bl	bl32_plat_enable_mmu
323
324#if SP_MIN_WITH_SECURE_FIQ
325	route_fiq_to_sp_min r0
326#endif
327
328	bl	sp_min_warm_boot
329	bl	smc_get_next_ctx
330	/* r0 points to `smc_ctx_t` */
331	/* The PSCI cpu_context registers have been copied to `smc_ctx_t` */
332
333#if ENABLE_RUNTIME_INSTRUMENTATION
334	/* Save smc_ctx_t */
335	mov	r5, r0
336
337	pmf_calc_timestamp_addr rt_instr_svc, RT_INSTR_EXIT_PSCI
338	mov	r4, r0
339
340	/*
341	 * Invalidate before updating timestamp to ensure previous timestamp
342	 * updates on the same cache line with caches disabled are properly
343	 * seen by the same core. Without the cache invalidate, the core might
344	 * write into a stale cache line.
345	 */
346	mov	r1, #PMF_TS_SIZE
347	bl	inv_dcache_range
348
349	ldcopr16 r0, r1, CNTPCT_64
350	strd	r0, r1, [r4]
351
352	/* Restore smc_ctx_t */
353	mov	r0, r5
354#endif
355
356	b	sp_min_exit
357endfunc sp_min_warm_entrypoint
358
359/*
360 * The function to restore the registers from SMC context and return
361 * to the mode restored to SPSR.
362 *
363 * Arguments : r0 must point to the SMC context to restore from.
364 */
365func sp_min_exit
366	monitor_exit
367endfunc sp_min_exit
368