Lines Matching refs:r0
18 ldcopr16 r0, r1, CORTEX_A72_ECTLR
19 orr64_imm r0, r1, CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT
20 bic64_imm r0, r1, (CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK | \
22 stcopr16 r0, r1, CORTEX_A72_ECTLR
32 ldcopr16 r0, r1, CORTEX_A72_CPUACTLR
33 orr64_imm r0, r1, CORTEX_A72_CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH
34 stcopr16 r0, r1, CORTEX_A72_CPUACTLR
46 ldcopr16 r0, r1, CORTEX_A72_ECTLR
47 bic64_imm r0, r1, CORTEX_A72_ECTLR_SMP_BIT
48 stcopr16 r0, r1, CORTEX_A72_ECTLR
57 mov r0, #1
58 stcopr r0, DBGOSDLR
76 cmp r0, #ERRATA_NOT_APPLIES
78 ldcopr16 r0, r1, CORTEX_A72_CPUACTLR
80 stcopr16 r0, r1, CORTEX_A72_CPUACTLR
93 mov r0, #ERRATA_MISSING
101 mov r0, #ERRATA_APPLIES
103 mov r0, #ERRATA_MISSING
111 mov r0, #ERRATA_MISSING
124 mov r4, r0
127 mov r0, r4
132 ldcopr16 r0, r1, CORTEX_A72_CPUACTLR
133 orr64_imm r0, r1, CORTEX_A72_CPUACTLR_DIS_LOAD_PASS_STORE
134 stcopr16 r0, r1, CORTEX_A72_CPUACTLR
143 ldcopr16 r0, r1, CORTEX_A72_ECTLR
144 orr64_imm r0, r1, CORTEX_A72_ECTLR_SMP_BIT
145 stcopr16 r0, r1, CORTEX_A72_ECTLR
159 ldcopr r0, SCTLR
160 tst r0, #SCTLR_C_BIT
180 mov r0, #DC_OP_CISW
206 ldcopr r0, SCTLR
207 tst r0, #SCTLR_C_BIT
228 mov r0, #DC_OP_CISW
242 mov r0, #DC_OP_CISW