| /Zephyr-latest/include/zephyr/sys/ |
| D | byteorder.h | 219 #define sys_le16_to_cpu(val) (val) argument
220 #define sys_cpu_to_le16(val) (val) argument
221 #define sys_le24_to_cpu(val) (val) argument
222 #define sys_cpu_to_le24(val) (val) argument
223 #define sys_le32_to_cpu(val) (val) argument
224 #define sys_cpu_to_le32(val) (val) argument
225 #define sys_le40_to_cpu(val) (val) argument
226 #define sys_cpu_to_le40(val) (val) argument
227 #define sys_le48_to_cpu(val) (val) argument
228 #define sys_cpu_to_le48(val) (val) argument
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| /Zephyr-latest/include/zephyr/dt-bindings/clock/ |
| D | stm32h5_clock.h | 76 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ argument
80 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
97 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, CCIPR1_REG) argument
98 #define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 3, CCIPR1_REG) argument
99 #define USART3_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 6, CCIPR1_REG) argument
100 #define USART4_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 9, CCIPR1_REG) argument
101 #define USART5_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 12, CCIPR1_REG) argument
102 #define USART6_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 15, CCIPR1_REG) argument
103 #define USART7_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 18, CCIPR1_REG) argument
104 #define USART8_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 21, CCIPR1_REG) argument
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| D | stm32u5_clock.h | 77 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ argument
81 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
96 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR1_REG) argument
97 #define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR1_REG) argument
98 #define USART3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, CCIPR1_REG) argument
99 #define UART4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 6, CCIPR1_REG) argument
100 #define UART5_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR1_REG) argument
101 #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR1_REG) argument
102 #define I2C2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR1_REG) argument
103 #define I2C4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 14, CCIPR1_REG) argument
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| D | stm32l4_clock.h | 62 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ argument
66 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
80 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG) argument
81 #define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR_REG) argument
82 #define USART3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, CCIPR_REG) argument
83 #define UART4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 6, CCIPR_REG) argument
84 #define UART5_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR_REG) argument
85 #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG) argument
86 #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG) argument
87 #define I2C2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 14, CCIPR_REG) argument
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| D | stm32h7_clock.h | 83 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ argument
87 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
103 #define FMC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, D1CCIPR_REG) argument
104 #define QSPI_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, D1CCIPR_REG) argument
105 #define DSI_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 8, D1CCIPR_REG) argument
106 #define SDMMC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 16, D1CCIPR_REG) argument
107 #define CKPER_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 28, D1CCIPR_REG) argument
109 #define OSPI_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, D1CCIPR_REG) argument
111 #define SAI1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, D2CCIP1R_REG) argument
112 #define SAI23_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 6, D2CCIP1R_REG) argument
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| D | stm32f7_clock.h | 66 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ argument
70 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
80 #define I2S_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 23, CFGR_REG) argument
81 #define MCO1_SEL(val) STM32_MCO_CFGR(val, 0x3, 21, CFGR_REG) argument
82 #define MCO1_PRE(val) STM32_MCO_CFGR(val, 0x7, 24, CFGR_REG) argument
83 #define MCO2_SEL(val) STM32_MCO_CFGR(val, 0x3, 30, CFGR_REG) argument
84 #define MCO2_PRE(val) STM32_MCO_CFGR(val, 0x7, 27, CFGR_REG) argument
94 #define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG) argument
102 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, DCKCFGR2_REG) argument
103 #define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, DCKCFGR2_REG) argument
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| D | stm32f3_clock.h | 56 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ argument
60 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
71 #define I2S_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 23, CFGR_REG) argument
72 #define MCO1_SEL(val) STM32_MCO_CFGR(val, 0x7, 24, CFGR_REG) argument
73 #define MCO1_PRE(val) STM32_MCO_CFGR(val, 0x7, 28, CFGR_REG) argument
75 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CFGR3_REG) argument
76 #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 4, CFGR3_REG) argument
77 #define I2C2_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 5, CFGR3_REG) argument
78 #define I2C3_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 6, CFGR3_REG) argument
79 #define TIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 8, CFGR3_REG) argument
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| D | stm32h7rs_clock.h | 79 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ argument
83 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
102 #define FMC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, D1CCIPR_REG) argument
103 #define SDMMC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 2, D1CCIPR_REG) argument
104 #define XSPI1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, D1CCIPR_REG) argument
105 #define XSPI2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 6, D1CCIPR_REG) argument
106 #define ADC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 24, D1CCIPR_REG) argument
107 #define CKPER_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 28, D1CCIPR_REG) argument
110 #define USART234578_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, D2CCIPR_REG) argument
111 #define SPI23_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 4, D2CCIPR_REG) argument
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| D | stm32g0_clock.h | 60 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ argument
64 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
75 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG) argument
76 #define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR_REG) argument
77 #define USART3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, CCIPR_REG) argument
78 #define CEC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 6, CCIPR_REG) argument
79 #define LPUART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR_REG) argument
80 #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG) argument
81 #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG) argument
82 #define I2C2_I2S1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 14, CCIPR_REG) argument
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| D | stm32g4_clock.h | 64 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ argument
68 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
79 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG) argument
80 #define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR_REG) argument
81 #define USART3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, CCIPR_REG) argument
82 #define USART4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 6, CCIPR_REG) argument
83 #define USART5_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR_REG) argument
84 #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG) argument
85 #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG) argument
86 #define I2C2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 14, CCIPR_REG) argument
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| D | stm32f410_clock.h | 15 #define CKDFSDM2A_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 14, DCKCFGR_REG) argument
16 #define CKDFSDM1A_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 15, DCKCFGR_REG) argument
17 #define SAI1A_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, DCKCFGR_REG) argument
18 #define SAI1B_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, DCKCFGR_REG) argument
19 #define I2S1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 25, DCKCFGR_REG) argument
20 #define I2S2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 27, DCKCFGR_REG) argument
21 #define CKDFSDM_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 31, DCKCFGR_REG) argument
24 #define I2CFMP1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, DCKCFGR2_REG) argument
25 #define CK48M_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 27, DCKCFGR2_REG) argument
26 #define SDIO_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 28, DCKCFGR2_REG) argument
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| D | stm32u0_clock.h | 61 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ argument
65 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
75 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG) argument
76 #define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR_REG) argument
77 #define LPUART3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 6, CCIPR_REG) argument
78 #define LPUART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR_REG) argument
79 #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG) argument
80 #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG) argument
81 #define I2C3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CCIPR_REG) argument
82 #define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR_REG) argument
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| D | stm32wl_clock.h | 63 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ argument
67 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
77 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG) argument
78 #define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR_REG) argument
79 #define SPI2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR_REG) argument
80 #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG) argument
81 #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG) argument
82 #define I2C2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 14, CCIPR_REG) argument
83 #define I2C3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CCIPR_REG) argument
84 #define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR_REG) argument
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| D | stm32wba_clock.h | 71 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ argument
75 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
86 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR1_REG) argument
87 #define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR1_REG) argument
88 #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR1_REG) argument
89 #define LPTIM2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR1_REG) argument
90 #define SPI1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR1_REG) argument
91 #define SYSTICK_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, CCIPR1_REG) argument
92 #define TIMIC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 31, CCIPR1_REG) argument
94 #define RNG_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR2_REG) argument
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| D | stm32wb_clock.h | 63 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ argument
67 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
80 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG) argument
81 #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG) argument
82 #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG) argument
83 #define I2C3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CCIPR_REG) argument
84 #define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR_REG) argument
85 #define LPTIM2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR_REG) argument
86 #define SAI1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, CCIPR_REG) argument
87 #define CLK48_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 26, CCIPR_REG) argument
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| D | stm32f0_clock.h | 55 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ argument
59 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
70 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CFGR3_REG) argument
71 #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 4, CFGR3_REG) argument
72 #define CEC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 6, CFGR3_REG) argument
73 #define USB_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 7, CFGR3_REG) argument
74 #define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CFGR3_REG) argument
75 #define USART3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CFGR3_REG) argument
77 #define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG) argument
80 #define MCO1_SEL(val) STM32_MCO_CFGR(val, 0xF, 24, CFGR1_REG) argument
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| D | stm32f427_clock.h | 14 #define CKDFSDM2A_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 14, DCKCFGR_REG) argument
15 #define CKDFSDM1A_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 15, DCKCFGR_REG) argument
16 #define SAI1A_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, DCKCFGR_REG) argument
17 #define SAI1B_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, DCKCFGR_REG) argument
18 #define CLK48M_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 27, DCKCFGR_REG) argument
19 #define SDMMC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 28, DCKCFGR_REG) argument
20 #define DSI_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 29, DCKCFGR_REG) argument
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| D | stm32c0_clock.h | 54 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ argument
58 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
71 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG) argument
72 #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG) argument
73 #define I2C2_I2S1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 14, CCIPR_REG) argument
74 #define ADC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 30, CCIPR_REG) argument
76 #define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, CSR1_REG) argument
79 #define MCO1_SEL(val) STM32_MCO_CFGR(val, 0x7, 24, CFGR1_REG) argument
80 #define MCO1_PRE(val) STM32_MCO_CFGR(val, 0x7, 28, CFGR1_REG) argument
81 #define MCO2_SEL(val) STM32_MCO_CFGR(val, 0x7, 16, CFGR1_REG) argument
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| D | stm32l0_clock.h | 56 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ argument
60 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
70 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG) argument
71 #define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR_REG) argument
72 #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG) argument
73 #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG) argument
74 #define I2C3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CCIPR_REG) argument
75 #define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR_REG) argument
76 #define HSI48_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 26, CCIPR_REG) argument
78 #define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CSR_REG) argument
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| /Zephyr-latest/lib/net_buf/ |
| D | buf_simple.c | 76 uint8_t *net_buf_simple_add_u8(struct net_buf_simple *buf, uint8_t val) in net_buf_simple_add_u8() argument
80 NET_BUF_SIMPLE_DBG("buf %p val 0x%02x", buf, val); in net_buf_simple_add_u8()
83 *u8 = val; in net_buf_simple_add_u8()
88 void net_buf_simple_add_le16(struct net_buf_simple *buf, uint16_t val) in net_buf_simple_add_le16() argument
90 NET_BUF_SIMPLE_DBG("buf %p val %u", buf, val); in net_buf_simple_add_le16()
92 sys_put_le16(val, net_buf_simple_add(buf, sizeof(val))); in net_buf_simple_add_le16()
95 void net_buf_simple_add_be16(struct net_buf_simple *buf, uint16_t val) in net_buf_simple_add_be16() argument
97 NET_BUF_SIMPLE_DBG("buf %p val %u", buf, val); in net_buf_simple_add_be16()
99 sys_put_be16(val, net_buf_simple_add(buf, sizeof(val))); in net_buf_simple_add_be16()
102 void net_buf_simple_add_le24(struct net_buf_simple *buf, uint32_t val) in net_buf_simple_add_le24() argument
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| /Zephyr-latest/drivers/fuel_gauge/bq27z746/ |
| D | emul_bq27z746.c | 110 static int emul_bq27z746_reg_read(const struct emul *target, int reg, int *val) in emul_bq27z746_reg_read() argument
114 *val = 1; in emul_bq27z746_reg_read()
117 *val = -2; in emul_bq27z746_reg_read()
120 *val = 1; in emul_bq27z746_reg_read()
123 *val = 1; in emul_bq27z746_reg_read()
126 *val = 1; in emul_bq27z746_reg_read()
129 *val = 1; in emul_bq27z746_reg_read()
132 *val = -2; in emul_bq27z746_reg_read()
135 *val = 1; in emul_bq27z746_reg_read()
138 *val = 1; in emul_bq27z746_reg_read()
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| /Zephyr-latest/drivers/audio/ |
| D | tas6422dac.c | 57 static void codec_write_reg(const struct device *dev, uint8_t reg, uint8_t val);
58 static void codec_read_reg(const struct device *dev, uint8_t reg, uint8_t *val);
121 uint8_t val; in codec_mute_output() local
131 codec_read_reg(dev, CH_STATE_CTRL_ADDR, &val); in codec_mute_output()
134 val &= ~CH_STATE_CTRL_CH1_STATE_CTRL_MASK; in codec_mute_output()
135 val |= CH_STATE_CTRL_CH1_STATE_CTRL(CH_STATE_CTRL_MUTE); in codec_mute_output()
138 val &= ~CH_STATE_CTRL_CH2_STATE_CTRL_MASK; in codec_mute_output()
139 val |= CH_STATE_CTRL_CH2_STATE_CTRL(CH_STATE_CTRL_MUTE); in codec_mute_output()
142 val &= ~(CH_STATE_CTRL_CH1_STATE_CTRL_MASK | CH_STATE_CTRL_CH2_STATE_CTRL_MASK); in codec_mute_output()
143 val |= CH_STATE_CTRL_CH1_STATE_CTRL(CH_STATE_CTRL_MUTE) | in codec_mute_output()
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| /Zephyr-latest/subsys/bluetooth/mesh/ |
| D | sar_cfg.c | 42 uint8_t val; in bt_mesh_sar_tx_decode() local
44 val = net_buf_simple_pull_u8(buf); in bt_mesh_sar_tx_decode()
45 tx->seg_int_step = (val & 0xf); in bt_mesh_sar_tx_decode()
46 tx->unicast_retrans_count = (val >> 4); in bt_mesh_sar_tx_decode()
47 val = net_buf_simple_pull_u8(buf); in bt_mesh_sar_tx_decode()
48 tx->unicast_retrans_without_prog_count = (val & 0xf); in bt_mesh_sar_tx_decode()
49 tx->unicast_retrans_int_step = (val >> 4); in bt_mesh_sar_tx_decode()
50 val = net_buf_simple_pull_u8(buf); in bt_mesh_sar_tx_decode()
51 tx->unicast_retrans_int_inc = (val & 0xf); in bt_mesh_sar_tx_decode()
52 tx->multicast_retrans_count = (val >> 4); in bt_mesh_sar_tx_decode()
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| /Zephyr-latest/lib/crc/ |
| D | crc8_sw.c | 21 uint8_t crc8_ccitt(uint8_t val, const void *buf, size_t cnt) in crc8_ccitt() argument
27 val ^= p[i]; in crc8_ccitt()
28 val = (val << 4) ^ crc8_ccitt_small_table[val >> 4]; in crc8_ccitt()
29 val = (val << 4) ^ crc8_ccitt_small_table[val >> 4]; in crc8_ccitt()
31 return val; in crc8_ccitt()
34 uint8_t crc8_rohc(uint8_t val, const void *buf, size_t cnt) in crc8_rohc() argument
40 val ^= p[i]; in crc8_rohc()
41 val = (val >> 4) ^ crc8_rohc_small_table[val & 0x0f]; in crc8_rohc()
42 val = (val >> 4) ^ crc8_rohc_small_table[val & 0x0f]; in crc8_rohc()
44 return val; in crc8_rohc()
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| /Zephyr-latest/include/zephyr/dt-bindings/dma/ |
| D | gd32_dma.h | 13 #define GD32_DMA_CH_CFG_DIRECTION(val) ((val & 0x3) << 6) argument
19 #define GD32_DMA_CH_CFG_PERIPH_ADDR_INC(val) ((val & 0x1) << 9) argument
24 #define GD32_DMA_CH_CFG_MEMORY_ADDR_INC(val) ((val & 0x1) << 10) argument
29 #define GD32_DMA_CH_CFG_PERIPH_WIDTH(val) ((val & 0x3) << 11) argument
35 #define GD32_DMA_CH_CFG_MEMORY_WIDTH(val) ((val & 0x3) << 13) argument
41 #define GD32_DMA_CH_CFG_PERIPH_INC_FIXED(val) ((val & 0x1) << 15) argument
44 #define GD32_DMA_CH_CFG_PRIORITY(val) ((val & 0x3) << 16) argument
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