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Searched refs:R_SYSTEM (Results 1 – 25 of 32) sorted by relevance

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/hal_renesas-latest/drivers/ra/fsp/src/bsp/mcu/all/
Dbsp_clocks.c757 if (operating_mode == R_SYSTEM->OPCCR) in bsp_prv_operating_mode_opccr_set()
763 if (0U == R_SYSTEM->HOCOCR) in bsp_prv_operating_mode_opccr_set()
766 FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.HOCOSF, 1U); in bsp_prv_operating_mode_opccr_set()
771 FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OPCCR_b.OPCMTSF, 0U); in bsp_prv_operating_mode_opccr_set()
774 R_SYSTEM->OPCCR = operating_mode; in bsp_prv_operating_mode_opccr_set()
777 FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OPCCR_b.OPCMTSF, 0U); in bsp_prv_operating_mode_opccr_set()
796 …if ((operating_mode > BSP_PRV_OPERATING_MODE_MIDDLE_SPEED) && (R_SYSTEM->DCDCCTL & R_SYSTEM_DCDCCT… in bsp_prv_operating_mode_set()
810 FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->SOPCCR_b.SOPCMTSF, 0U); in bsp_prv_operating_mode_set()
813 R_SYSTEM->SOPCCR = 0x1U; in bsp_prv_operating_mode_set()
816 FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->SOPCCR_b.SOPCMTSF, 0U); in bsp_prv_operating_mode_set()
[all …]
Dbsp_register_protection.c76 …R_SYSTEM->PRCR_NS = ((R_SYSTEM->PRCR_NS | BSP_PRV_PRCR_KEY) & (uint16_t) (~g_prcr_masks[regs_to_pr… in R_BSP_RegisterProtectEnable()
78 …R_SYSTEM->PRCR = ((R_SYSTEM->PRCR | BSP_PRV_PRCR_KEY) & (uint16_t) (~g_prcr_masks[regs_to_protect]… in R_BSP_RegisterProtectEnable()
106 … R_SYSTEM->PRCR_NS = ((R_SYSTEM->PRCR_NS | BSP_PRV_PRCR_KEY) | g_prcr_masks[regs_to_unprotect]); in R_BSP_RegisterProtectDisable()
108 R_SYSTEM->PRCR = ((R_SYSTEM->PRCR | BSP_PRV_PRCR_KEY) | g_prcr_masks[regs_to_unprotect]); in R_BSP_RegisterProtectDisable()
Dbsp_common.h361 uint32_t sckdivcr = FSP_STYPE3_REG32_READ(R_SYSTEM->SCKDIVCR, BSP_CFG_CLOCKS_SECURE); in R_FSP_SystemClockHzGet()
371 …uint32_t cpuclk_div = FSP_STYPE3_REG8_READ(R_SYSTEM->SCKDIVCR2, BSP_CFG_CLOCKS_SECURE) & FSP_PRV_S… in R_FSP_SystemClockHzGet()
449 uint32_t scispidivcr = R_SYSTEM->SCISPICKDIVCR; in R_FSP_SciSpiClockHzGet()
451 …fsp_priv_source_clock_t scispicksel = (fsp_priv_source_clock_t) R_SYSTEM->SCISPICKCR_b.SCISPICKSEL; in R_FSP_SciSpiClockHzGet()
466 …uint32_t spidivcr = FSP_STYPE3_REG8_READ(R_SYSTEM->SPICKDIVCR, BSP_CFG_CLOCKS_SECU… in R_FSP_SpiClockHzGet()
469 (fsp_priv_source_clock_t) ((FSP_STYPE3_REG8_READ(R_SYSTEM->SPICKCR, in R_FSP_SpiClockHzGet()
486 …uint32_t scidivcr = FSP_STYPE3_REG8_READ(R_SYSTEM->SCICKDIVCR, BSP_CFG_CLOCKS_SECU… in R_FSP_SciClockHzGet()
489 (fsp_priv_source_clock_t) (FSP_STYPE3_REG8_READ(R_SYSTEM->SCICKCR, in R_FSP_SciClockHzGet()
Dbsp_sdram.c78 R_SYSTEM->SDCKOCR = 1;
177 if (0 == R_SYSTEM->SDCKOCR)
181 R_SYSTEM->SDCKOCR = 1;
Dbsp_module_stop.h25 #define R_BSP_MSTPCRA (R_SYSTEM->MSTPCRA)
/hal_renesas-latest/drivers/ra/fsp/src/r_lpm/
Dr_lpm.c25 #define LPM_CLOCK_HOCOCR (&R_SYSTEM->HOCOCR)
26 #define LPM_CLOCK_MOCOCR (&R_SYSTEM->MOCOCR)
27 #define LPM_CLOCK_LOCOCR (&R_SYSTEM->LOCOCR)
28 #define LPM_CLOCK_MOSCCR (&R_SYSTEM->MOSCCR)
29 #define LPM_CLOCK_SOSCCR (&R_SYSTEM->SOSCCR)
30 #define LPM_CLOCK_PLLCR (&R_SYSTEM->PLLCR)
31 #define LPM_CLOCK_PLL2CR (&R_SYSTEM->PLL2CR)
239 FSP_ERROR_RETURN(0 == FSP_STYPE3_REG8_READ(R_SYSTEM->MOCOCR, !R_SYSTEM->CGFSAR_b.NONSEC03), in R_LPM_LowPowerModeEnter()
255 R_SYSTEM->LPSCR = r_lpm_lpscr_calculate(p_ctrl->p_cfg); in R_LPM_LowPowerModeEnter()
261 R_SYSTEM->SBYCR |= (1U << R_SYSTEM_SBYCR_SSBY_Pos); in R_LPM_LowPowerModeEnter()
[all …]
/hal_renesas-latest/drivers/ra/fsp/src/bsp/mcu/ra2l1/
Dbsp_power.c41 R_SYSTEM->DCDCCTL = (uint8_t) mode; in bsp_power_dcdc_disable()
61 uint8_t dcdcctl = R_SYSTEM->DCDCCTL | R_SYSTEM_DCDCCTL_STOPZA_Msk; in bsp_power_dcdc_enable()
62 R_SYSTEM->DCDCCTL = dcdcctl; in bsp_power_dcdc_enable()
65 R_SYSTEM->DCDCCTL = dcdcctl & (uint8_t) (~R_SYSTEM_DCDCCTL_PD_Msk); in bsp_power_dcdc_enable()
71 R_SYSTEM->DCDCCTL = 0x10; in bsp_power_dcdc_enable()
77 R_SYSTEM->DCDCCTL = 0x11; in bsp_power_dcdc_enable()
83 R_SYSTEM->DCDCCTL = 0x13; in bsp_power_dcdc_enable()
113 bsp_power_mode_t previous_mode = R_SYSTEM->DCDCCTL & R_SYSTEM_DCDCCTL_DCDCON_Msk ? in R_BSP_PowerModeSet()
114 (bsp_power_mode_t) R_SYSTEM->VCCSEL : BSP_POWER_MODE_LDO; in R_BSP_PowerModeSet()
124 R_SYSTEM->VCCSEL = (uint8_t) mode; in R_BSP_PowerModeSet()
/hal_renesas-latest/zephyr/ra/portable/
Dbsp_common.h363 uint32_t sckdivcr = FSP_STYPE3_REG32_READ(R_SYSTEM->SCKDIVCR, BSP_CFG_CLOCKS_SECURE); in R_FSP_SystemClockHzGet()
373 …uint32_t cpuclk_div = FSP_STYPE3_REG8_READ(R_SYSTEM->SCKDIVCR2, BSP_CFG_CLOCKS_SECURE) & FSP_PRV_S… in R_FSP_SystemClockHzGet()
451 uint32_t scispidivcr = R_SYSTEM->SCISPICKDIVCR; in R_FSP_SciSpiClockHzGet()
453 …fsp_priv_source_clock_t scispicksel = (fsp_priv_source_clock_t) R_SYSTEM->SCISPICKCR_b.SCISPICKSEL; in R_FSP_SciSpiClockHzGet()
468 …uint32_t spidivcr = FSP_STYPE3_REG8_READ(R_SYSTEM->SPICKDIVCR, BSP_CFG_CLOCKS_SECU… in R_FSP_SpiClockHzGet()
471 (fsp_priv_source_clock_t) ((FSP_STYPE3_REG8_READ(R_SYSTEM->SPICKCR, in R_FSP_SpiClockHzGet()
488 …uint32_t scidivcr = FSP_STYPE3_REG8_READ(R_SYSTEM->SCICKDIVCR, BSP_CFG_CLOCKS_SECU… in R_FSP_SciClockHzGet()
491 (fsp_priv_source_clock_t) (FSP_STYPE3_REG8_READ(R_SYSTEM->SCICKCR, in R_FSP_SciClockHzGet()
/hal_renesas-latest/drivers/ra/fsp/src/r_canfd/
Dr_canfd.c203 (FSP_STYPE3_REG8_READ(R_SYSTEM->CANFDCKCR, in R_CANFD_Open()
204 … !R_SYSTEM->CGFSAR_b.NONSEC18) == BSP_CLOCKS_SOURCE_CLOCK_PLL ? in R_CANFD_Open()
205 FSP_STYPE3_REG8_READ(R_SYSTEM->PLLCR, !R_SYSTEM->CGFSAR_b.NONSEC08) : in R_CANFD_Open()
206 FSP_STYPE3_REG8_READ(R_SYSTEM->PLL2CR, !R_SYSTEM->CGFSAR_b.NONSEC09)), in R_CANFD_Open()
/hal_renesas-latest/drivers/rz/fsp/src/rzg/r_gpt/
Dr_gpt.c1043 uint32_t divider = R_SYSTEM->GPTCKDIVCR; in R_GPT_PwmOutputDelayInitialize()
1055 …uint32_t gpt_frequency = R_BSP_SourceClockHzGet((fsp_priv_source_clock_t) R_SYSTEM->GPTCKCR_b.GPTC… in R_GPT_PwmOutputDelayInitialize()
/hal_renesas-latest/drivers/ra/fsp/src/r_gpt/
Dr_gpt.c1101 uint32_t divider = R_SYSTEM->GPTCKDIVCR; in R_GPT_PwmOutputDelayInitialize()
1113 …uint32_t gpt_frequency = R_BSP_SourceClockHzGet((fsp_priv_source_clock_t) R_SYSTEM->GPTCKCR_b.GPTC… in R_GPT_PwmOutputDelayInitialize()
/hal_renesas-latest/drivers/ra/fsp/src/r_iic_master/
Dr_iic_master.c823 volatile uint32_t sysdiccr = FSP_STYPE3_REG8_READ(R_SYSTEM->SCKDIVCR, BSP_CFG_CLOCKS_SECURE); in iic_master_run_hw_master()
/hal_renesas-latest/drivers/ra/fsp/src/r_flash_hp/
Dr_flash_hp.c1727 R_SYSTEM->FWEPROR = 0x01U; in flash_hp_init()
/hal_renesas-latest/drivers/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/
DR7FA2L1AB.h12423 #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) macro
DR7FA2A1AB.h13775 #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) macro
DR7FA4E10D.h13634 #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) macro
DR7FA4W1AD.h13750 #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) macro
DR7FA4M1AB.h13916 #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) macro
DR7FA4M2AD.h14638 #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) macro
DR7FA4M3AF.h14742 #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) macro
DR7FA4E2B9.h15962 #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) macro
DR7FA6E10F.h15123 #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) macro
DR7FA6M1AD.h15459 #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) macro
DR7FA6E2BB.h16168 #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) macro
DR7FA6M4AF.h16823 #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) macro

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