1 /* 2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef BSP_MODULE_H 8 #define BSP_MODULE_H 9 10 /** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ 11 FSP_HEADER 12 13 /*******************************************************************************************************************//** 14 * @addtogroup BSP_MCU 15 * @{ 16 **********************************************************************************************************************/ 17 18 #if BSP_FEATURE_TZ_HAS_TRUSTZONE 19 20 /* MSTPCRA is located in R_MSTP for Star devices. */ 21 #define R_BSP_MSTPCRA (R_MSTP->MSTPCRA) 22 #else 23 24 /* MSTPCRA is located in R_SYSTEM for W1D and Peaks devices. */ 25 #define R_BSP_MSTPCRA (R_SYSTEM->MSTPCRA) 26 #endif 27 28 /*******************************************************************************************************************//** 29 * Cancels the module stop state. 30 * 31 * @param ip fsp_ip_t enum value for the module to be stopped 32 * @param channel The channel. Use channel 0 for modules without channels. 33 **********************************************************************************************************************/ 34 #if BSP_CFG_MSTP_CHANGE_DELAY_ENABLE 35 #define R_BSP_MODULE_START(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ 36 FSP_CRITICAL_SECTION_ENTER; \ 37 BSP_MSTP_REG_ ## ip(channel) &= ~BSP_MSTP_BIT_ ## ip(channel); \ 38 FSP_REGISTER_READ(BSP_MSTP_REG_ ## ip(channel)); \ 39 R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, \ 40 BSP_DELAY_UNITS_MICROSECONDS); \ 41 FSP_CRITICAL_SECTION_EXIT;} 42 #else 43 #define R_BSP_MODULE_START(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ 44 FSP_CRITICAL_SECTION_ENTER; \ 45 BSP_MSTP_REG_ ## ip(channel) &= \ 46 (BSP_MSTP_REG_TYPE_ ## ip(channel)) ~BSP_MSTP_BIT_ ## ip(channel); \ 47 FSP_REGISTER_READ(BSP_MSTP_REG_ ## ip(channel)); \ 48 FSP_CRITICAL_SECTION_EXIT;} 49 #endif 50 51 /*******************************************************************************************************************//** 52 * Enables the module stop state. 53 * 54 * @param ip fsp_ip_t enum value for the module to be stopped 55 * @param channel The channel. Use channel 0 for modules without channels. 56 **********************************************************************************************************************/ 57 #if BSP_CFG_MSTP_CHANGE_DELAY_ENABLE 58 #define R_BSP_MODULE_STOP(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ 59 FSP_CRITICAL_SECTION_ENTER; \ 60 BSP_MSTP_REG_ ## ip(channel) |= BSP_MSTP_BIT_ ## ip(channel); \ 61 FSP_REGISTER_READ(BSP_MSTP_REG_ ## ip(channel)); \ 62 R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, \ 63 BSP_DELAY_UNITS_MICROSECONDS); \ 64 FSP_CRITICAL_SECTION_EXIT;} 65 #else 66 #define R_BSP_MODULE_STOP(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ 67 FSP_CRITICAL_SECTION_ENTER; \ 68 BSP_MSTP_REG_ ## ip(channel) |= BSP_MSTP_BIT_ ## ip(channel); \ 69 FSP_REGISTER_READ(BSP_MSTP_REG_ ## ip(channel)); \ 70 FSP_CRITICAL_SECTION_EXIT;} 71 #endif 72 73 /** @} (end addtogroup BSP_MCU) */ 74 75 #if 0U == BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE 76 #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRD 77 #define BSP_MSTP_BIT_FSP_IP_GPT(channel) ((BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH >= \ 78 channel) ? (1U << 5U) : (1U << 6U)); 79 #define BSP_MSTP_REG_TYPE_FSP_IP_GPT(channel) uint32_t 80 81 #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD 82 83 #if BSP_MCU_GROUP_RA2A2 84 85 /* RA2A2 has a combination of AGT and AGTW. 86 * Ch 0-1: MSTPD[ 3: 2] (AGTW0, AGTW1) 87 * Ch 2-3: MSTPD[19:18] (AGT0, AGT1) 88 * Ch 4-5: MSTPD[ 1: 0] (AGT2, AGT3) 89 * Ch 6-9: MSTPD[10: 7] (AGT4, AGT5, AGT6, AGT7) 90 */ 91 #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << \ 92 ((channel < BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT) \ 93 ? (3U - channel) \ 94 : ((channel < BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + 2U) \ 95 ? (19U - channel + BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT) \ 96 : ((channel < BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + 4U) \ 97 ? (1U - channel + BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + 2U) \ 98 : (10U - channel + BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + \ 99 4U))))); 100 101 #else 102 #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel)); 103 #endif 104 #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t 105 106 #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD 107 #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U)); 108 #define BSP_MSTP_REG_TYPE_FSP_IP_POEG(channel) uint32_t 109 #else 110 #if (2U == BSP_FEATURE_ELC_VERSION) 111 #if BSP_MCU_GROUP_RA6T2 112 #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE 113 #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << 31); 114 #define BSP_MSTP_REG_TYPE_FSP_IP_GPT(channel) uint32_t 115 #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD 116 #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel)); 117 #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t 118 #else 119 #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE 120 #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel)); 121 #define BSP_MSTP_REG_TYPE_FSP_IP_GPT(channel) uint32_t 122 #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD 123 #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (5U - channel)); 124 #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t 125 #endif 126 #define BSP_MSTP_REG_FSP_IP_KEY(channel) R_MSTP->MSTPCRE 127 #define BSP_MSTP_BIT_FSP_IP_KEY(channel) (1U << 4U); 128 #define BSP_MSTP_REG_TYPE_FSP_IP_KEY(channel) uint32_t 129 #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD 130 #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel)); 131 #define BSP_MSTP_REG_TYPE_FSP_IP_POEG(channel) uint32_t 132 #define BSP_MSTP_REG_FSP_IP_ULPT(channel) R_MSTP->MSTPCRE 133 #define BSP_MSTP_BIT_FSP_IP_ULPT(channel) (1U << (9U - channel)); 134 #define BSP_MSTP_REG_TYPE_FSP_IP_ULPT(channel) uint32_t 135 #else 136 #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE 137 #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel)); 138 #define BSP_MSTP_REG_TYPE_FSP_IP_GPT(channel) uint32_t 139 #define BSP_MSTP_REG_FSP_IP_AGT(channel) *((3U >= channel) ? &R_MSTP->MSTPCRD : &R_MSTP->MSTPCRE) 140 #define BSP_MSTP_BIT_FSP_IP_AGT(channel) ((3U >= \ 141 channel) ? (1U << (3U - channel)) : (1U << \ 142 (15U - (channel - 4U)))); 143 #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t 144 #define BSP_MSTP_REG_FSP_IP_KEY(channel) R_MSTP->MSTPCRE 145 #define BSP_MSTP_BIT_FSP_IP_KEY(channel) (1U << (4U - channel)); 146 #define BSP_MSTP_REG_TYPE_FSP_IP_KEY(channel) uint32_t 147 #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD 148 #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel)); 149 #define BSP_MSTP_REG_TYPE_FSP_IP_POEG(channel) uint32_t 150 #endif 151 #endif 152 153 #define BSP_MSTP_REG_FSP_IP_DMAC(channel) R_BSP_MSTPCRA 154 #define BSP_MSTP_BIT_FSP_IP_DMAC(channel) (1U << (22U)); 155 #define BSP_MSTP_REG_TYPE_FSP_IP_DMAC(channel) uint32_t 156 #if BSP_FEATURE_CGC_REGISTER_SET_B 157 #define BSP_MSTP_REG_FSP_IP_DTC(channel) R_BSP_MSTPCRA 158 #define BSP_MSTP_BIT_FSP_IP_DTC(channel) (1U << (6U)) 159 #define BSP_MSTP_REG_TYPE_FSP_IP_DTC(channel) uint16_t 160 #else 161 #define BSP_MSTP_REG_FSP_IP_DTC(channel) R_BSP_MSTPCRA 162 #define BSP_MSTP_BIT_FSP_IP_DTC(channel) (1U << (22U)); 163 #define BSP_MSTP_REG_TYPE_FSP_IP_DTC(channel) uint32_t 164 #endif 165 #define BSP_MSTP_REG_FSP_IP_CAN(channel) R_MSTP->MSTPCRB 166 #define BSP_MSTP_BIT_FSP_IP_CAN(channel) (1U << (2U - channel)); 167 #define BSP_MSTP_REG_TYPE_FSP_IP_CAN(channel) uint32_t 168 #define BSP_MSTP_REG_FSP_IP_CEC(channel) R_MSTP->MSTPCRB 169 #define BSP_MSTP_BIT_FSP_IP_CEC(channel) (1U << (3U)); 170 #define BSP_MSTP_REG_TYPE_FSP_IP_CEC(channel) uint32_t 171 #define BSP_MSTP_REG_FSP_IP_I3C(channel) R_MSTP->MSTPCRB 172 #define BSP_MSTP_BIT_FSP_IP_I3C(channel) (1U << (BSP_FEATURE_I3C_MSTP_OFFSET - channel)); 173 #define BSP_MSTP_REG_TYPE_FSP_IP_I3C(channel) uint32_t 174 #define BSP_MSTP_REG_FSP_IP_IRDA(channel) R_MSTP->MSTPCRB 175 #define BSP_MSTP_BIT_FSP_IP_IRDA(channel) (1U << (5U - channel)); 176 #define BSP_MSTP_REG_TYPE_FSP_IP_IRDA(channel) uint32_t 177 #define BSP_MSTP_REG_FSP_IP_QSPI(channel) R_MSTP->MSTPCRB 178 #define BSP_MSTP_BIT_FSP_IP_QSPI(channel) (1U << (6U - channel)); 179 #define BSP_MSTP_REG_TYPE_FSP_IP_QSPI(channel) uint32_t 180 #define BSP_MSTP_REG_FSP_IP_SAU(channel) R_MSTP->MSTPCRB 181 #define BSP_MSTP_BIT_FSP_IP_SAU(channel) (1U << (6U + channel)); 182 #define BSP_MSTP_REG_TYPE_FSP_IP_SAU(channel) uint32_t 183 #define BSP_MSTP_REG_FSP_IP_IIC(channel) R_MSTP->MSTPCRB 184 #define BSP_MSTP_BIT_FSP_IP_IIC(channel) (1U << (9U - channel)); 185 #define BSP_MSTP_REG_TYPE_FSP_IP_IIC(channel) uint32_t 186 #define BSP_MSTP_REG_FSP_IP_IICA(channel) R_MSTP->MSTPCRB 187 #define BSP_MSTP_BIT_FSP_IP_IICA(channel) (1U << (10U)); 188 #define BSP_MSTP_REG_TYPE_FSP_IP_IICA(channel) uint32_t 189 #define BSP_MSTP_REG_FSP_IP_USBFS(channel) R_MSTP->MSTPCRB 190 #define BSP_MSTP_BIT_FSP_IP_USBFS(channel) (1U << (11U - channel)); 191 #define BSP_MSTP_REG_TYPE_FSP_IP_USBFS(channel) uint32_t 192 #define BSP_MSTP_REG_FSP_IP_USBHS(channel) R_MSTP->MSTPCRB 193 #define BSP_MSTP_BIT_FSP_IP_USBHS(channel) (1U << (12U - channel)); 194 #define BSP_MSTP_REG_TYPE_FSP_IP_USBHS(channel) uint32_t 195 #define BSP_MSTP_REG_FSP_IP_EPTPC(channel) R_MSTP->MSTPCRB 196 #define BSP_MSTP_BIT_FSP_IP_EPTPC(channel) (1U << (13U - channel)); 197 #define BSP_MSTP_REG_TYPE_FSP_IP_EPTPC(channel) uint32_t 198 #define BSP_MSTP_REG_FSP_IP_ETHER(channel) R_MSTP->MSTPCRB 199 #define BSP_MSTP_BIT_FSP_IP_ETHER(channel) (1U << (15U - channel)); 200 #define BSP_MSTP_REG_TYPE_FSP_IP_ETHER(channel) uint32_t 201 #define BSP_MSTP_REG_FSP_IP_UARTA(channel) R_MSTP->MSTPCRB 202 #define BSP_MSTP_BIT_FSP_IP_UARTA(channel) (1U << (15U)); 203 #define BSP_MSTP_REG_TYPE_FSP_IP_UARTA(channel) uint32_t 204 #define BSP_MSTP_REG_FSP_IP_OSPI(channel) R_MSTP->MSTPCRB 205 #define BSP_MSTP_BIT_FSP_IP_OSPI(channel) (1U << (16U - channel)); 206 #define BSP_MSTP_REG_TYPE_FSP_IP_OSPI(channel) uint32_t 207 #define BSP_MSTP_REG_FSP_IP_SPI(channel) R_MSTP->MSTPCRB 208 #define BSP_MSTP_BIT_FSP_IP_SPI(channel) (1U << (19U - channel)); 209 #define BSP_MSTP_REG_TYPE_FSP_IP_SPI(channel) uint32_t 210 #define BSP_MSTP_REG_FSP_IP_SCI(channel) R_MSTP->MSTPCRB 211 #define BSP_MSTP_REG_TYPE_FSP_IP_SCI(channel) uint32_t 212 #define BSP_MSTP_BIT_FSP_IP_SCI(channel) (1U << (31U - channel)); 213 #define BSP_MSTP_REG_FSP_IP_CAC(channel) R_MSTP->MSTPCRC 214 #define BSP_MSTP_REG_TYPE_FSP_IP_CAC(channel) uint32_t 215 #define BSP_MSTP_BIT_FSP_IP_CAC(channel) (1U << (0U - channel)); 216 #define BSP_MSTP_REG_FSP_IP_CRC(channel) R_MSTP->MSTPCRC 217 #define BSP_MSTP_REG_TYPE_FSP_IP_CRC(channel) uint32_t 218 #define BSP_MSTP_BIT_FSP_IP_CRC(channel) (1U << (1U - channel)); 219 #define BSP_MSTP_REG_FSP_IP_PDC(channel) R_MSTP->MSTPCRC 220 #define BSP_MSTP_BIT_FSP_IP_PDC(channel) (1U << (2U - channel)); 221 #define BSP_MSTP_REG_TYPE_FSP_IP_PDC(channel) uint32_t 222 #define BSP_MSTP_REG_FSP_IP_CTSU(channel) R_MSTP->MSTPCRC 223 #define BSP_MSTP_BIT_FSP_IP_CTSU(channel) (1U << (3U - channel)); 224 #define BSP_MSTP_REG_TYPE_FSP_IP_CTSU(channel) uint32_t 225 #define BSP_MSTP_REG_FSP_IP_SLCDC(channel) R_MSTP->MSTPCRC 226 #define BSP_MSTP_BIT_FSP_IP_SLCDC(channel) (1U << (4U - channel)); 227 #define BSP_MSTP_REG_TYPE_FSP_IP_SLCDC(channel) uint32_t 228 #define BSP_MSTP_REG_FSP_IP_GLCDC(channel) R_MSTP->MSTPCRC 229 #define BSP_MSTP_BIT_FSP_IP_GLCDC(channel) (1U << (4U - channel)); 230 #define BSP_MSTP_REG_TYPE_FSP_IP_GLCDC(channel) uint32_t 231 #define BSP_MSTP_REG_FSP_IP_JPEG(channel) R_MSTP->MSTPCRC 232 #define BSP_MSTP_BIT_FSP_IP_JPEG(channel) (1U << (5U - channel)); 233 #define BSP_MSTP_REG_TYPE_FSP_IP_JPEG(channel) uint32_t 234 #define BSP_MSTP_REG_FSP_IP_DRW(channel) R_MSTP->MSTPCRC 235 #define BSP_MSTP_BIT_FSP_IP_DRW(channel) (1U << (6U - channel)); 236 #define BSP_MSTP_REG_TYPE_FSP_IP_DRW(channel) uint32_t 237 #define BSP_MSTP_REG_FSP_IP_SSI(channel) R_MSTP->MSTPCRC 238 #define BSP_MSTP_BIT_FSP_IP_SSI(channel) (1U << (8U - channel)); 239 #define BSP_MSTP_REG_TYPE_FSP_IP_SSI(channel) uint32_t 240 #define BSP_MSTP_REG_FSP_IP_SRC(channel) R_MSTP->MSTPCRC 241 #define BSP_MSTP_BIT_FSP_IP_SRC(channel) (1U << (9U - channel)); 242 #define BSP_MSTP_REG_TYPE_FSP_IP_SRC(channel) uint32_t 243 #define BSP_MSTP_REG_FSP_IP_MIPI_DSI(channel) R_MSTP->MSTPCRC 244 #define BSP_MSTP_BIT_FSP_IP_MIPI_DSI(channel) (1U << (10U - channel)); 245 #define BSP_MSTP_REG_TYPE_FSP_IP_MIPI_DSI(channel) uint32_t 246 #define BSP_MSTP_REG_FSP_IP_SDHIMMC(channel) R_MSTP->MSTPCRC 247 #define BSP_MSTP_BIT_FSP_IP_SDHIMMC(channel) (1U << (12U - channel)); 248 #define BSP_MSTP_REG_TYPE_FSP_IP_SDHIMMC(channel) uint32_t 249 #define BSP_MSTP_REG_FSP_IP_DOC(channel) R_MSTP->MSTPCRC 250 #define BSP_MSTP_BIT_FSP_IP_DOC(channel) (1U << (13U - channel)); 251 #define BSP_MSTP_REG_TYPE_FSP_IP_DOC(channel) uint32_t 252 #define BSP_MSTP_REG_FSP_IP_ELC(channel) R_MSTP->MSTPCRC 253 #define BSP_MSTP_BIT_FSP_IP_ELC(channel) (1U << (14U - channel)); 254 #define BSP_MSTP_REG_TYPE_FSP_IP_ELC(channel) uint32_t 255 #define BSP_MSTP_REG_FSP_IP_MACL(channel) R_MSTP->MSTPCRC 256 #define BSP_MSTP_BIT_FSP_IP_MACL(channel) (1U << (15U - channel)); 257 #define BSP_MSTP_REG_TYPE_FSP_IP_MACL(channel) uint32_t 258 #define BSP_MSTP_REG_FSP_IP_CEU(channel) R_MSTP->MSTPCRC 259 #define BSP_MSTP_REG_TYPE_FSP_IP_CEU(channel) uint32_t 260 #define BSP_MSTP_BIT_FSP_IP_CEU(channel) (1U << (16U - channel)); 261 #define BSP_MSTP_REG_FSP_IP_TFU(channel) R_MSTP->MSTPCRC 262 #define BSP_MSTP_BIT_FSP_IP_TFU(channel) (1U << (20U - channel)); 263 #define BSP_MSTP_REG_TYPE_FSP_IP_TFU(channel) uint32_t 264 #define BSP_MSTP_REG_FSP_IP_IIRFA(channel) R_MSTP->MSTPCRC 265 #define BSP_MSTP_BIT_FSP_IP_IIRFA(channel) (1U << (21U - channel)); 266 #define BSP_MSTP_REG_TYPE_FSP_IP_IIRFA(channel) uint32_t 267 #define BSP_MSTP_REG_FSP_IP_CANFD(channel) R_MSTP->MSTPCRC 268 #define BSP_MSTP_BIT_FSP_IP_CANFD(channel) (1U << (27U - channel)); 269 #define BSP_MSTP_REG_TYPE_FSP_IP_CANFD(channel) uint32_t 270 #define BSP_MSTP_REG_FSP_IP_TRNG(channel) R_MSTP->MSTPCRC 271 #define BSP_MSTP_BIT_FSP_IP_TRNG(channel) (1U << (28U - channel)); 272 #define BSP_MSTP_REG_TYPE_FSP_IP_TRNG(channel) uint32_t 273 #define BSP_MSTP_REG_FSP_IP_SCE(channel) R_MSTP->MSTPCRC 274 #define BSP_MSTP_BIT_FSP_IP_SCE(channel) (1U << (31U - channel)); 275 #define BSP_MSTP_REG_TYPE_FSP_IP_SCE(channel) uint32_t 276 #define BSP_MSTP_REG_FSP_IP_AES(channel) R_MSTP->MSTPCRC 277 #define BSP_MSTP_BIT_FSP_IP_AES(channel) (1U << (31U - channel)); 278 #define BSP_MSTP_REG_TYPE_FSP_IP_AES(channel) uint32_t 279 #define BSP_MSTP_REG_FSP_IP_TAU(channel) R_MSTP->MSTPCRD 280 #define BSP_MSTP_BIT_FSP_IP_TAU(channel) (1U << (0U)); 281 #define BSP_MSTP_REG_TYPE_FSP_IP_TAU(channel) uint32_t 282 #define BSP_MSTP_REG_FSP_IP_TML(channel) R_MSTP->MSTPCRD 283 #define BSP_MSTP_BIT_FSP_IP_TML(channel) (1U << (4U)); 284 #define BSP_MSTP_REG_TYPE_FSP_IP_TML(channel) uint32_t 285 #define BSP_MSTP_REG_FSP_IP_ADC(channel) R_MSTP->MSTPCRD 286 #define BSP_MSTP_BIT_FSP_IP_ADC(channel) (1U << (16U - channel)); 287 #define BSP_MSTP_REG_TYPE_FSP_IP_ADC(channel) uint32_t 288 #define BSP_MSTP_REG_FSP_IP_SDADC(channel) R_MSTP->MSTPCRD 289 #define BSP_MSTP_BIT_FSP_IP_SDADC(channel) (1U << (17U - channel)); 290 #define BSP_MSTP_REG_TYPE_FSP_IP_SDADC(channel) uint32_t 291 #if (BSP_FEATURE_DAC_MAX_CHANNELS > 2U) 292 #define BSP_MSTP_REG_FSP_IP_DAC(channel) R_MSTP->MSTPCRD 293 #define BSP_MSTP_BIT_FSP_IP_DAC(channel) (1U << (20U - channel)); 294 #define BSP_MSTP_REG_TYPE_FSP_IP_DAC(channel) uint32_t 295 #else 296 #define BSP_MSTP_REG_FSP_IP_DAC8(channel) R_MSTP->MSTPCRD 297 #define BSP_MSTP_BIT_FSP_IP_DAC8(channel) (1U << (19U)); 298 #define BSP_MSTP_REG_TYPE_FSP_IP_DAC8(channel) uint32_t 299 #define BSP_MSTP_REG_FSP_IP_DAC(channel) R_MSTP->MSTPCRD 300 #define BSP_MSTP_BIT_FSP_IP_DAC(channel) (1U << (20U)); 301 #define BSP_MSTP_REG_TYPE_FSP_IP_DAC(channel) uint32_t 302 #endif 303 #define BSP_MSTP_REG_FSP_IP_TSN(channel) R_MSTP->MSTPCRD 304 #define BSP_MSTP_BIT_FSP_IP_TSN(channel) (1U << (22U - channel)); 305 #define BSP_MSTP_REG_TYPE_FSP_IP_TSN(channel) uint32_t 306 #define BSP_MSTP_REG_FSP_IP_RTC(channel) R_MSTP->MSTPCRD 307 #define BSP_MSTP_BIT_FSP_IP_RTC(channel) (1U << (23U)); 308 #define BSP_MSTP_REG_TYPE_FSP_IP_RTC(channel) uint32_t 309 #define BSP_MSTP_REG_FSP_IP_ACMPHS(channel) R_MSTP->MSTPCRD 310 #define BSP_MSTP_BIT_FSP_IP_ACMPHS(channel) (1U << (28U - channel)); 311 #define BSP_MSTP_REG_TYPE_FSP_IP_ACMPHS(channel) uint32_t 312 #define BSP_MSTP_REG_FSP_IP_ACMPLP(channel) R_MSTP->MSTPCRD 313 #define BSP_MSTP_BIT_FSP_IP_ACMPLP(channel) (1U << 29U); 314 #define BSP_MSTP_REG_TYPE_FSP_IP_ACMPLP(channel) uint32_t 315 #define BSP_MSTP_REG_FSP_IP_OPAMP(channel) R_MSTP->MSTPCRD 316 #define BSP_MSTP_BIT_FSP_IP_OPAMP(channel) (1U << (31U - channel)); 317 #define BSP_MSTP_REG_TYPE_FSP_IP_OPAMP(channel) uint32_t 318 #if (1U == BSP_FEATURE_CGC_HAS_OSTDCSE) 319 #define BSP_MSTP_REG_FSP_IP_SOSTD(channel) R_BSP_MSTPCRA 320 #define BSP_MSTP_BIT_FSP_IP_SOSTD(channel) (1U << (16U)); 321 #define BSP_MSTP_REG_TYPE_FSP_IP_SOSTD(channel) uint32_t 322 #define BSP_MSTP_REG_FSP_IP_MOSTD(channel) R_BSP_MSTPCRA 323 #define BSP_MSTP_BIT_FSP_IP_MOSTD(channel) (1U << (17U)); 324 #define BSP_MSTP_REG_TYPE_FSP_IP_MOSTD(channel) uint32_t 325 #endif 326 327 /** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ 328 FSP_FOOTER 329 330 #endif 331
