1 /*
2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #ifndef BSP_COMMON_H
8 #define BSP_COMMON_H
9
10 /***********************************************************************************************************************
11 * Includes <System Includes> , "Project Includes"
12 **********************************************************************************************************************/
13
14 /* C99 includes. */
15 #include <stdint.h>
16 #include <stddef.h>
17 #include <stdbool.h>
18 #include <assert.h>
19 #include <string.h>
20
21 /* Different compiler support. */
22 #include "../../inc/api/fsp_common_api.h"
23 #include "bsp_compiler_support.h"
24
25 /* BSP TFU Includes. */
26 #include "../../src/bsp/mcu/all/bsp_tfu.h"
27
28 #include "bsp_cfg.h"
29
30 /** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
31 FSP_HEADER
32
33 /*******************************************************************************************************************//**
34 * @addtogroup BSP_MCU
35 * @{
36 **********************************************************************************************************************/
37
38 /***********************************************************************************************************************
39 * Macro definitions
40 **********************************************************************************************************************/
41
42 /** Used to signify that an ELC event is not able to be used as an interrupt. */
43 #define BSP_IRQ_DISABLED (0xFFU)
44
45 /* Version of this module's code and API. */
46
47 #if 1 == BSP_CFG_RTOS /* ThreadX */
48 #include "tx_user.h"
49 #if defined(TX_ENABLE_EVENT_TRACE) || defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY)
50 #include "tx_port.h"
51 #define FSP_CONTEXT_SAVE tx_isr_start((uint32_t) R_FSP_CurrentIrqGet());
52 #define FSP_CONTEXT_RESTORE tx_isr_end((uint32_t) R_FSP_CurrentIrqGet());
53 #else
54 #define FSP_CONTEXT_SAVE
55 #define FSP_CONTEXT_RESTORE
56 #endif
57 #else
58 #define FSP_CONTEXT_SAVE
59 #define FSP_CONTEXT_RESTORE
60 #endif
61
62 /** Macro that can be defined in order to enable logging in FSP modules. */
63 #ifndef FSP_LOG_PRINT
64 #define FSP_LOG_PRINT(X)
65 #endif
66
67 /** Macro to log and return error without an assertion. */
68 #ifndef FSP_RETURN
69
70 #define FSP_RETURN(err) FSP_ERROR_LOG((err)); \
71 return err;
72 #endif
73
74 /** This function is called before returning an error code. To stop on a runtime error, define fsp_error_log in
75 * user code and do required debugging (breakpoints, stack dump, etc) in this function.*/
76 #if (1 == BSP_CFG_ERROR_LOG)
77
78 #ifndef FSP_ERROR_LOG
79 #define FSP_ERROR_LOG(err) \
80 fsp_error_log((err), __FILE__, __LINE__);
81 #endif
82 #else
83
84 #define FSP_ERROR_LOG(err)
85 #endif
86
87 /** Default assertion calls ::FSP_ERROR_RETURN if condition "a" is false. Used to identify incorrect use of API's in FSP
88 * functions. */
89 #if (3 == BSP_CFG_ASSERT)
90 #define FSP_ASSERT(a)
91 #elif (2 == BSP_CFG_ASSERT)
92 #define FSP_ASSERT(a) {assert(a);}
93 #else
94 #define FSP_ASSERT(a) FSP_ERROR_RETURN((a), FSP_ERR_ASSERTION)
95 #endif // ifndef FSP_ASSERT
96
97 /** All FSP error codes are returned using this macro. Calls ::FSP_ERROR_LOG function if condition "a" is false. Used
98 * to identify runtime errors in FSP functions. */
99
100 #define FSP_ERROR_RETURN(a, err) \
101 { \
102 if ((a)) \
103 { \
104 (void) 0; /* Do nothing */ \
105 } \
106 else \
107 { \
108 FSP_ERROR_LOG(err); \
109 return err; \
110 } \
111 }
112
113 /* Function-like macro used to wait for a condition to be met, most often used to wait for hardware register updates.
114 * This macro can be redefined to add a timeout if necessary. */
115 #ifndef FSP_HARDWARE_REGISTER_WAIT
116 #define FSP_HARDWARE_REGISTER_WAIT(reg, required_value) while (reg != required_value) { /* Wait. */}
117 #endif
118
119 #ifndef FSP_REGISTER_READ
120
121 /* Read a register and discard the result. */
122 #define FSP_REGISTER_READ(A) __ASM volatile ("" : : "r" (A));
123 #endif
124
125 /****************************************************************
126 *
127 * This check is performed to select suitable ASM API with respect to core
128 *
129 * The macros __CORE__ , __ARM7EM__ and __ARM_ARCH_8M_BASE__ are undefined for GCC, but defined(__IAR_SYSTEMS_ICC__) is false for GCC, so
130 * the left half of the || expression evaluates to false for GCC regardless of the values of these macros. */
131
132 #if (defined(__IAR_SYSTEMS_ICC__) && ((__CORE__ == __ARM7EM__) || (__CORE__ == __ARM_ARCH_8M_BASE__))) || \
133 defined(__ARM_ARCH_7EM__) // CM4
134 #ifndef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION
135 #define BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION (0U)
136 #endif
137 #else // CM23
138 #ifdef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION
139 #undef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION
140 #endif
141 #define BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION (0U)
142 #endif
143
144 /* This macro defines a variable for saving previous mask value */
145 #ifndef FSP_CRITICAL_SECTION_DEFINE
146
147 #define FSP_CRITICAL_SECTION_DEFINE uint32_t old_mask_level = 0U
148 #endif
149
150 /* These macros abstract methods to save and restore the interrupt state for different architectures. */
151 #if (0 == BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION)
152 #define FSP_CRITICAL_SECTION_GET_CURRENT_STATE __get_PRIMASK
153 #define FSP_CRITICAL_SECTION_SET_STATE __set_PRIMASK
154 #define FSP_CRITICAL_SECTION_IRQ_MASK_SET (1U)
155 #else
156 #define FSP_CRITICAL_SECTION_GET_CURRENT_STATE __get_BASEPRI
157 #define FSP_CRITICAL_SECTION_SET_STATE __set_BASEPRI
158 #define FSP_CRITICAL_SECTION_IRQ_MASK_SET ((uint8_t) (BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION << \
159 (8U - __NVIC_PRIO_BITS)))
160 #endif
161
162 /** This macro temporarily saves the current interrupt state and disables interrupts. */
163 #ifndef FSP_CRITICAL_SECTION_ENTER
164 #define FSP_CRITICAL_SECTION_ENTER \
165 old_mask_level = FSP_CRITICAL_SECTION_GET_CURRENT_STATE(); \
166 FSP_CRITICAL_SECTION_SET_STATE(FSP_CRITICAL_SECTION_IRQ_MASK_SET)
167 #endif
168
169 /** This macro restores the previously saved interrupt state, reenabling interrupts. */
170 #ifndef FSP_CRITICAL_SECTION_EXIT
171 #define FSP_CRITICAL_SECTION_EXIT FSP_CRITICAL_SECTION_SET_STATE(old_mask_level)
172 #endif
173
174 /* Number of Cortex processor exceptions, used as an offset from XPSR value for the IRQn_Type macro. */
175 #define FSP_PRIV_CORTEX_PROCESSOR_EXCEPTIONS (16U)
176
177 /** Used to signify that the requested IRQ vector is not defined in this system. */
178 #define FSP_INVALID_VECTOR ((IRQn_Type) - 33)
179
180 /* Private definition used in bsp_clocks and R_FSP_SystemClockHzGet. Each bitfield in SCKDIVCR is up to 4 bits wide. */
181 #if (BSP_CFG_MCU_PART_SERIES == 8)
182 #define FSP_PRV_SCKDIVCR_DIV_MASK (0xFU)
183 #else
184 #define FSP_PRV_SCKDIVCR_DIV_MASK (0x7U)
185 #endif
186
187 /* Use the secure registers for secure projects and flat projects. */
188 #if !BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_HAS_TRUSTZONE
189 #define FSP_PRIV_TZ_USE_SECURE_REGS (1)
190 #else
191 #define FSP_PRIV_TZ_USE_SECURE_REGS (0)
192 #endif
193
194 /* Put certain BSP variables in uninitialized RAM when initializing BSP early. */
195 #if BSP_CFG_EARLY_INIT
196 #define BSP_SECTION_EARLY_INIT BSP_PLACE_IN_SECTION(BSP_SECTION_NOINIT)
197 #else
198 #define BSP_SECTION_EARLY_INIT
199 #endif
200
201 #if (BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD) && BSP_FEATURE_TZ_VERSION == 2
202 BSP_CMSE_NONSECURE_ENTRY uint8_t R_BSP_NSC_STYPE3_RegU8Read(uint8_t volatile const * p_reg);
203 BSP_CMSE_NONSECURE_ENTRY uint16_t R_BSP_NSC_STYPE3_RegU16Read(uint16_t volatile const * p_reg);
204 BSP_CMSE_NONSECURE_ENTRY uint32_t R_BSP_NSC_STYPE3_RegU32Read(uint32_t volatile const * p_reg);
205
206 #endif
207
208 #if BSP_FEATURE_TZ_HAS_TRUSTZONE && BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_VERSION == 2
209
210 /*
211 * If the STYPE3 register's security attribution is set to secure, the non-secure application must read the register
212 * from the secure application using the provided non-secure callable functions.
213 */
214 #define FSP_STYPE3_REG8_READ(X, S) (!(S) ? X : (R_BSP_NSC_STYPE3_RegU8Read((uint8_t const volatile *) &X)))
215 #define FSP_STYPE3_REG16_READ(X, S) (!(S) ? X : (R_BSP_NSC_STYPE3_RegU16Read((uint16_t const volatile *) &X)))
216 #define FSP_STYPE3_REG32_READ(X, S) (!(S) ? X : (R_BSP_NSC_STYPE3_RegU32Read((uint32_t const volatile *) &X)))
217 #elif BSP_FEATURE_TZ_HAS_TRUSTZONE && BSP_TZ_SECURE_BUILD && BSP_FEATURE_TZ_VERSION == 2
218
219 /*******************************************************************************************************************//**
220 * Read a non-secure 8-bit STYPE3 register in the secure state.
221 *
222 * @param[in] p_reg The address of the non-secure register.
223 *
224 * @return Value read from the register.
225 **********************************************************************************************************************/
R_BSP_S_STYPE3_RegU8Read(uint8_t volatile const * p_reg)226 __STATIC_INLINE uint8_t R_BSP_S_STYPE3_RegU8Read (uint8_t volatile const * p_reg)
227 {
228 p_reg = (uint8_t volatile const *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET);
229
230 return *p_reg;
231 }
232
233 /*******************************************************************************************************************//**
234 * Read a non-secure 16-bit STYPE3 register in the secure state.
235 *
236 * @param[in] p_reg The address of the non-secure register.
237 *
238 * @return Value read from the register.
239 **********************************************************************************************************************/
R_BSP_S_STYPE3_RegU16Read(uint16_t volatile const * p_reg)240 __STATIC_INLINE uint16_t R_BSP_S_STYPE3_RegU16Read (uint16_t volatile const * p_reg)
241 {
242 p_reg = (uint16_t volatile const *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET);
243
244 return *p_reg;
245 }
246
247 /*******************************************************************************************************************//**
248 * Read a non-secure 32-bit STYPE3 register in the secure state.
249 *
250 * @param[in] p_reg The address of the non-secure register.
251 *
252 * @return Value read from the register.
253 **********************************************************************************************************************/
R_BSP_S_STYPE3_RegU32Read(uint32_t volatile const * p_reg)254 __STATIC_INLINE uint32_t R_BSP_S_STYPE3_RegU32Read (uint32_t volatile const * p_reg)
255 {
256 p_reg = (uint32_t volatile const *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET);
257
258 return *p_reg;
259 }
260
261 /*
262 * If the STYPE3 register's security attribution is set to non-secure, the secure application must read the register
263 * using the non-secure aliased address.
264 */
265 #define FSP_STYPE3_REG8_READ(X, S) ((S) ? (X) : R_BSP_S_STYPE3_RegU8Read((uint8_t const volatile *) &X))
266 #define FSP_STYPE3_REG16_READ(X, S) ((S) ? (X) : R_BSP_S_STYPE3_RegU16Read((uint16_t const volatile *) &X))
267 #define FSP_STYPE3_REG32_READ(X, S) ((S) ? (X) : R_BSP_S_STYPE3_RegU32Read((uint32_t const volatile *) &X))
268 #else
269 #define FSP_STYPE3_REG8_READ(X, S) (X)
270 #define FSP_STYPE3_REG16_READ(X, S) (X)
271 #define FSP_STYPE3_REG32_READ(X, S) (X)
272 #endif
273
274 /***********************************************************************************************************************
275 * Typedef definitions
276 **********************************************************************************************************************/
277
278 /** Different warm start entry locations in the BSP. */
279 typedef enum e_bsp_warm_start_event
280 {
281 BSP_WARM_START_RESET = 0, ///< Called almost immediately after reset. No C runtime environment, clocks, or IRQs.
282 BSP_WARM_START_POST_CLOCK, ///< Called after clock initialization. No C runtime environment or IRQs.
283 BSP_WARM_START_POST_C ///< Called after clocks and C runtime environment have been set up
284 } bsp_warm_start_event_t;
285
286 /* Private enum used in R_FSP_SystemClockHzGet. Maps clock name to base bit in SCKDIVCR. */
287 typedef enum e_fsp_priv_clock
288 {
289 FSP_PRIV_CLOCK_PCLKD = 0,
290 FSP_PRIV_CLOCK_PCLKC = 4,
291 FSP_PRIV_CLOCK_PCLKB = 8,
292 FSP_PRIV_CLOCK_PCLKA = 12,
293 FSP_PRIV_CLOCK_BCLK = 16,
294 FSP_PRIV_CLOCK_PCLKE = 20,
295 FSP_PRIV_CLOCK_ICLK = 24,
296 FSP_PRIV_CLOCK_FCLK = 28,
297 FSP_PRIV_CLOCK_CPUCLK = 32,
298 } fsp_priv_clock_t;
299
300 /* Private enum used in R_FSP_SciSpiClockHzGe. Maps clock name to base bit in SCISPICKCR. */
301 typedef enum e_fsp_priv_source_clock
302 {
303 FSP_PRIV_CLOCK_HOCO = 0, ///< The high speed on chip oscillator
304 FSP_PRIV_CLOCK_MOCO = 1, ///< The middle speed on chip oscillator
305 FSP_PRIV_CLOCK_LOCO = 2, ///< The low speed on chip oscillator
306 FSP_PRIV_CLOCK_MAIN_OSC = 3, ///< The main oscillator
307 FSP_PRIV_CLOCK_SUBCLOCK = 4, ///< The subclock oscillator
308 FSP_PRIV_CLOCK_PLL = 5, ///< The PLL output
309 FSP_PRIV_CLOCK_PLL1P = 5, ///< The PLL1P output
310 FSP_PRIV_CLOCK_PLL2 = 6, ///< The PLL2 output
311 FSP_PRIV_CLOCK_PLL2P = 6, ///< The PLL2P output
312 FSP_PRIV_CLOCK_PLL1Q = 7, ///< The PLL1Q output
313 FSP_PRIV_CLOCK_PLL1R = 8, ///< The PLL1R output
314 FSP_PRIV_CLOCK_PLL2Q = 9, ///< The PLL2Q output
315 FSP_PRIV_CLOCK_PLL2R = 10, ///< The PLL2R output
316 } fsp_priv_source_clock_t;
317
318 typedef struct st_bsp_unique_id
319 {
320 union
321 {
322 uint32_t unique_id_words[4];
323 uint8_t unique_id_bytes[16];
324 };
325 } bsp_unique_id_t;
326
327 /***********************************************************************************************************************
328 * Exported global variables
329 **********************************************************************************************************************/
330 uint32_t R_BSP_SourceClockHzGet(fsp_priv_source_clock_t clock);
331
332 /***********************************************************************************************************************
333 * Global variables (defined in other files)
334 **********************************************************************************************************************/
335
336 /***********************************************************************************************************************
337 * Inline Functions
338 **********************************************************************************************************************/
339
340 /*******************************************************************************************************************//**
341 * Return active interrupt vector number value
342 *
343 * @return Active interrupt vector number value
344 **********************************************************************************************************************/
R_FSP_CurrentIrqGet(void)345 __STATIC_INLINE IRQn_Type R_FSP_CurrentIrqGet (void)
346 {
347 xPSR_Type xpsr_value;
348 xpsr_value.w = __get_xPSR();
349
350 return (IRQn_Type) (xpsr_value.b.ISR - FSP_PRIV_CORTEX_PROCESSOR_EXCEPTIONS);
351 }
352
353 /*******************************************************************************************************************//**
354 * Gets the frequency of a system clock.
355 *
356 * @return Frequency of requested clock in Hertz.
357 **********************************************************************************************************************/
R_FSP_SystemClockHzGet(fsp_priv_clock_t clock)358 __STATIC_INLINE uint32_t R_FSP_SystemClockHzGet (fsp_priv_clock_t clock)
359 {
360 #if !BSP_FEATURE_CGC_REGISTER_SET_B
361 uint32_t sckdivcr = FSP_STYPE3_REG32_READ(R_SYSTEM->SCKDIVCR, BSP_CFG_CLOCKS_SECURE);
362 uint32_t clock_div = (sckdivcr >> clock) & FSP_PRV_SCKDIVCR_DIV_MASK;
363
364 #if BSP_FEATURE_CGC_HAS_CPUCLK
365 if (FSP_PRIV_CLOCK_CPUCLK == clock)
366 {
367 return SystemCoreClock;
368 }
369
370 /* Get CPUCLK divisor */
371 uint32_t cpuclk_div = FSP_STYPE3_REG8_READ(R_SYSTEM->SCKDIVCR2, BSP_CFG_CLOCKS_SECURE) & FSP_PRV_SCKDIVCR_DIV_MASK;
372
373 /* Determine if either divisor is a multiple of 3 */
374 if ((cpuclk_div | clock_div) & 8U)
375 {
376 /* Convert divisor settings to their actual values */
377 cpuclk_div = (cpuclk_div & 8U) ? (3U << (cpuclk_div & 7U)) : (1U << cpuclk_div);
378 clock_div = (clock_div & 8U) ? (3U << (clock_div & 7U)) : (1U << clock_div);
379
380 /* Calculate clock with multiplication and division instead of shifting */
381 return (SystemCoreClock * cpuclk_div) / clock_div;
382 }
383 else
384 {
385 return (SystemCoreClock << cpuclk_div) >> clock_div;
386 }
387
388 #else
389 uint32_t iclk_div = (sckdivcr >> FSP_PRIV_CLOCK_ICLK) & FSP_PRV_SCKDIVCR_DIV_MASK;
390
391 return (SystemCoreClock << iclk_div) >> clock_div;
392 #endif
393 #else
394 FSP_PARAMETER_NOT_USED(clock);
395
396 return SystemCoreClock;
397 #endif
398 }
399
400 /*******************************************************************************************************************//**
401 * Converts a clock's CKDIVCR register value to a clock divider (Eg: SPICKDIVCR).
402 *
403 * @return Clock Divider
404 **********************************************************************************************************************/
R_FSP_ClockDividerGet(uint32_t ckdivcr)405 __STATIC_INLINE uint32_t R_FSP_ClockDividerGet (uint32_t ckdivcr)
406 {
407 if (2U >= ckdivcr)
408 {
409
410 /* clock_div:
411 * - Clock Divided by 1: 0
412 * - Clock Divided by 2: 1
413 * - Clock Divided by 4: 2
414 */
415 return 1U << ckdivcr;
416 }
417 else if (3U == ckdivcr)
418 {
419
420 /* Clock Divided by 6 */
421 return 6U;
422 }
423 else if (4U == ckdivcr)
424 {
425
426 /* Clock Divided by 8 */
427 return 8U;
428 }
429 else if (5U == ckdivcr)
430 {
431
432 /* Clock Divided by 3 */
433 return 3U;
434 }
435
436 /* Clock Divided by 5 */
437 return 5U;
438 }
439
440 #if BSP_FEATURE_BSP_HAS_SCISPI_CLOCK
441
442 /*******************************************************************************************************************//**
443 * Gets the frequency of a SCI/SPI clock.
444 *
445 * @return Frequency of requested clock in Hertz.
446 **********************************************************************************************************************/
R_FSP_SciSpiClockHzGet(void)447 __STATIC_INLINE uint32_t R_FSP_SciSpiClockHzGet (void)
448 {
449 uint32_t scispidivcr = R_SYSTEM->SCISPICKDIVCR;
450 uint32_t clock_div = R_FSP_ClockDividerGet(scispidivcr & FSP_PRV_SCKDIVCR_DIV_MASK);
451 fsp_priv_source_clock_t scispicksel = (fsp_priv_source_clock_t) R_SYSTEM->SCISPICKCR_b.SCISPICKSEL;
452
453 return R_BSP_SourceClockHzGet(scispicksel) / clock_div;
454 }
455
456 #endif
457 #if BSP_FEATURE_BSP_HAS_SPI_CLOCK
458
459 /*******************************************************************************************************************//**
460 * Gets the frequency of a SPI clock.
461 *
462 * @return Frequency of requested clock in Hertz.
463 **********************************************************************************************************************/
R_FSP_SpiClockHzGet(void)464 __STATIC_INLINE uint32_t R_FSP_SpiClockHzGet (void)
465 {
466 uint32_t spidivcr = FSP_STYPE3_REG8_READ(R_SYSTEM->SPICKDIVCR, BSP_CFG_CLOCKS_SECURE);
467 uint32_t clock_div = R_FSP_ClockDividerGet(spidivcr & FSP_PRV_SCKDIVCR_DIV_MASK);
468 fsp_priv_source_clock_t spicksel =
469 (fsp_priv_source_clock_t) ((FSP_STYPE3_REG8_READ(R_SYSTEM->SPICKCR,
470 BSP_CFG_CLOCKS_SECURE) & R_SYSTEM_SPICKCR_CKSEL_Msk) >>
471 R_SYSTEM_SPICKCR_CKSEL_Pos);
472
473 return R_BSP_SourceClockHzGet(spicksel) / clock_div;
474 }
475
476 #endif
477 #if BSP_FEATURE_BSP_HAS_SCI_CLOCK
478
479 /*******************************************************************************************************************//**
480 * Gets the frequency of a SCI clock.
481 *
482 * @return Frequency of requested clock in Hertz.
483 **********************************************************************************************************************/
R_FSP_SciClockHzGet(void)484 __STATIC_INLINE uint32_t R_FSP_SciClockHzGet (void)
485 {
486 uint32_t scidivcr = FSP_STYPE3_REG8_READ(R_SYSTEM->SCICKDIVCR, BSP_CFG_CLOCKS_SECURE);
487 uint32_t clock_div = R_FSP_ClockDividerGet(scidivcr & FSP_PRV_SCKDIVCR_DIV_MASK);
488 fsp_priv_source_clock_t scicksel =
489 (fsp_priv_source_clock_t) (FSP_STYPE3_REG8_READ(R_SYSTEM->SCICKCR,
490 BSP_CFG_CLOCKS_SECURE) & R_SYSTEM_SCICKCR_SCICKSEL_Msk >>
491 R_SYSTEM_SCICKCR_SCICKSEL_Pos);
492
493 return R_BSP_SourceClockHzGet(scicksel) / clock_div;
494 }
495
496 #endif
497
498 /*******************************************************************************************************************//**
499 * Get unique ID for this device.
500 *
501 * @return A pointer to the unique identifier structure
502 **********************************************************************************************************************/
R_BSP_UniqueIdGet(void)503 __STATIC_INLINE bsp_unique_id_t const * R_BSP_UniqueIdGet (void)
504 {
505 #if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_NONSECURE_BUILD == 1
506
507 return (bsp_unique_id_t *) (BSP_FEATURE_BSP_UNIQUE_ID_POINTER | BSP_FEATURE_TZ_NS_OFFSET);
508 #else
509
510 return (bsp_unique_id_t *) BSP_FEATURE_BSP_UNIQUE_ID_POINTER;
511 #endif
512 }
513
514 /*******************************************************************************************************************//**
515 * Disables the flash cache.
516 **********************************************************************************************************************/
R_BSP_FlashCacheDisable(void)517 __STATIC_INLINE void R_BSP_FlashCacheDisable (void)
518 {
519 #if BSP_FEATURE_BSP_FLASH_CACHE
520 R_FCACHE->FCACHEE = 0U;
521 #endif
522
523 #if BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE
524
525 /* Disable the C-Cache. */
526 R_CACHE->CCACTL = 0U;
527 #endif
528 }
529
530 /*******************************************************************************************************************//**
531 * Enables the flash cache.
532 **********************************************************************************************************************/
R_BSP_FlashCacheEnable(void)533 __STATIC_INLINE void R_BSP_FlashCacheEnable (void)
534 {
535 #if BSP_FEATURE_BSP_FLASH_CACHE
536
537 /* Invalidate the flash cache and wait until it is invalidated. (See section 55.3.2.2 "Operation" of the Flash Cache
538 * in the RA6M3 manual R01UH0878EJ0100). */
539 R_FCACHE->FCACHEIV = 1U;
540 FSP_HARDWARE_REGISTER_WAIT(R_FCACHE->FCACHEIV, 0U);
541
542 /* Enable flash cache. */
543 R_FCACHE->FCACHEE = 1U;
544 #endif
545
546 #if BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE
547
548 /* Configure the C-Cache line size. */
549 R_CACHE->CCALCF = BSP_CFG_C_CACHE_LINE_SIZE;
550
551 /* Enable the C-Cache. */
552 R_CACHE->CCACTL = 1U;
553 #endif
554 }
555
556 /***********************************************************************************************************************
557 * Exported global functions (to be accessed by other files)
558 **********************************************************************************************************************/
559 #if ((1 == BSP_CFG_ERROR_LOG) || (1 == BSP_CFG_ASSERT))
560
561 /** Prototype of default function called before errors are returned in FSP code if BSP_CFG_LOG_ERRORS is set to 1. */
562 void fsp_error_log(fsp_err_t err, const char * file, int32_t line);
563
564 #endif
565
566 /** In the event of an unrecoverable error the BSP will by default call the __BKPT() intrinsic function which will
567 * alert the user of the error. The user can override this default behavior by defining their own
568 * BSP_CFG_HANDLE_UNRECOVERABLE_ERROR macro.
569 */
570 #if !defined(BSP_CFG_HANDLE_UNRECOVERABLE_ERROR)
571
572 #define BSP_CFG_HANDLE_UNRECOVERABLE_ERROR(x) __BKPT((x))
573 #endif
574
575 /** @} (end addtogroup BSP_MCU) */
576
577 /** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
578 FSP_FOOTER
579
580 #endif
581
