1 /*
2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #ifndef BSP_COMMON_H
8 #define BSP_COMMON_H
9
10 /***********************************************************************************************************************
11 * Includes <System Includes> , "Project Includes"
12 **********************************************************************************************************************/
13
14 /* C99 includes. */
15 #include <stdint.h>
16 #include <stddef.h>
17 #include <stdbool.h>
18 #include <assert.h>
19 #include <string.h>
20
21 /* Different compiler support. */
22 #include "fsp_common_api.h"
23 #include "bsp_compiler_support.h"
24
25 /* BSP TFU Includes. */
26 #include "bsp_tfu.h"
27
28 #include "bsp_sdram.h"
29
30 #include "bsp_cfg.h"
31
32 /** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
33 FSP_HEADER
34
35 /*******************************************************************************************************************//**
36 * @addtogroup BSP_MCU
37 * @{
38 **********************************************************************************************************************/
39
40 /***********************************************************************************************************************
41 * Macro definitions
42 **********************************************************************************************************************/
43
44 /** Used to signify that an ELC event is not able to be used as an interrupt. */
45 #define BSP_IRQ_DISABLED (0xFFU)
46
47 /* Version of this module's code and API. */
48
49 #if 1 == BSP_CFG_RTOS /* ThreadX */
50 #include "tx_user.h"
51 #if defined(TX_ENABLE_EVENT_TRACE) || defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY)
52 #include "tx_port.h"
53 #define FSP_CONTEXT_SAVE tx_isr_start((uint32_t) R_FSP_CurrentIrqGet());
54 #define FSP_CONTEXT_RESTORE tx_isr_end((uint32_t) R_FSP_CurrentIrqGet());
55 #else
56 #define FSP_CONTEXT_SAVE
57 #define FSP_CONTEXT_RESTORE
58 #endif
59 #else
60 #define FSP_CONTEXT_SAVE
61 #define FSP_CONTEXT_RESTORE
62 #endif
63
64 /** Macro that can be defined in order to enable logging in FSP modules. */
65 #ifndef FSP_LOG_PRINT
66 #define FSP_LOG_PRINT(X)
67 #endif
68
69 /** Macro to log and return error without an assertion. */
70 #ifndef FSP_RETURN
71
72 #define FSP_RETURN(err) FSP_ERROR_LOG((err)); \
73 return err;
74 #endif
75
76 /** This function is called before returning an error code. To stop on a runtime error, define fsp_error_log in
77 * user code and do required debugging (breakpoints, stack dump, etc) in this function.*/
78 #if (1 == BSP_CFG_ERROR_LOG)
79
80 #ifndef FSP_ERROR_LOG
81 #define FSP_ERROR_LOG(err) \
82 fsp_error_log((err), __FILE__, __LINE__);
83 #endif
84 #else
85
86 #define FSP_ERROR_LOG(err)
87 #endif
88
89 /** Default assertion calls ::FSP_ERROR_RETURN if condition "a" is false. Used to identify incorrect use of API's in FSP
90 * functions. */
91 #if (3 == BSP_CFG_ASSERT)
92 #define FSP_ASSERT(a)
93 #elif (2 == BSP_CFG_ASSERT)
94 #define FSP_ASSERT(a) {assert(a);}
95 #else
96 #define FSP_ASSERT(a) FSP_ERROR_RETURN((a), FSP_ERR_ASSERTION)
97 #endif // ifndef FSP_ASSERT
98
99 /** All FSP error codes are returned using this macro. Calls ::FSP_ERROR_LOG function if condition "a" is false. Used
100 * to identify runtime errors in FSP functions. */
101
102 #define FSP_ERROR_RETURN(a, err) \
103 { \
104 if ((a)) \
105 { \
106 (void) 0; /* Do nothing */ \
107 } \
108 else \
109 { \
110 FSP_ERROR_LOG(err); \
111 return err; \
112 } \
113 }
114
115 /* Function-like macro used to wait for a condition to be met, most often used to wait for hardware register updates.
116 * This macro can be redefined to add a timeout if necessary. */
117 #ifndef FSP_HARDWARE_REGISTER_WAIT
118 #define FSP_HARDWARE_REGISTER_WAIT(reg, required_value) while (reg != required_value) { /* Wait. */}
119 #endif
120
121 #ifndef FSP_REGISTER_READ
122
123 /* Read a register and discard the result. */
124 #define FSP_REGISTER_READ(A) __ASM volatile ("" : : "r" (A));
125 #endif
126
127 /****************************************************************
128 *
129 * This check is performed to select suitable ASM API with respect to core
130 *
131 * The macros __CORE__ , __ARM7EM__ and __ARM_ARCH_8M_BASE__ are undefined for GCC, but defined(__IAR_SYSTEMS_ICC__) is false for GCC, so
132 * the left half of the || expression evaluates to false for GCC regardless of the values of these macros. */
133
134 #if (defined(__IAR_SYSTEMS_ICC__) && ((__CORE__ == __ARM7EM__) || (__CORE__ == __ARM_ARCH_8M_BASE__))) || \
135 defined(__ARM_ARCH_7EM__) // CM4
136 #ifndef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION
137 #define BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION (0U)
138 #endif
139 #else // CM23
140 #ifdef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION
141 #undef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION
142 #endif
143 #define BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION (0U)
144 #endif
145
146 /* This macro defines a variable for saving previous mask value */
147 #ifndef FSP_CRITICAL_SECTION_DEFINE
148
149 #define FSP_CRITICAL_SECTION_DEFINE uint32_t old_mask_level = 0U
150 #endif
151
152 /* These macros abstract methods to save and restore the interrupt state for different architectures. */
153 #if (0 == BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION)
154 #define FSP_CRITICAL_SECTION_GET_CURRENT_STATE __get_PRIMASK
155 #define FSP_CRITICAL_SECTION_SET_STATE __set_PRIMASK
156 #define FSP_CRITICAL_SECTION_IRQ_MASK_SET (1U)
157 #else
158 #define FSP_CRITICAL_SECTION_GET_CURRENT_STATE __get_BASEPRI
159 #define FSP_CRITICAL_SECTION_SET_STATE __set_BASEPRI
160 #define FSP_CRITICAL_SECTION_IRQ_MASK_SET ((uint8_t) (BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION << \
161 (8U - __NVIC_PRIO_BITS)))
162 #endif
163
164 /** This macro temporarily saves the current interrupt state and disables interrupts. */
165 #ifndef FSP_CRITICAL_SECTION_ENTER
166 #define FSP_CRITICAL_SECTION_ENTER \
167 old_mask_level = FSP_CRITICAL_SECTION_GET_CURRENT_STATE(); \
168 FSP_CRITICAL_SECTION_SET_STATE(FSP_CRITICAL_SECTION_IRQ_MASK_SET)
169 #endif
170
171 /** This macro restores the previously saved interrupt state, reenabling interrupts. */
172 #ifndef FSP_CRITICAL_SECTION_EXIT
173 #define FSP_CRITICAL_SECTION_EXIT FSP_CRITICAL_SECTION_SET_STATE(old_mask_level)
174 #endif
175
176 /* Number of Cortex processor exceptions, used as an offset from XPSR value for the IRQn_Type macro. */
177 #define FSP_PRIV_CORTEX_PROCESSOR_EXCEPTIONS (16U)
178
179 /** Used to signify that the requested IRQ vector is not defined in this system. */
180 #define FSP_INVALID_VECTOR ((IRQn_Type) - 33)
181
182 /* Private definition used in bsp_clocks and R_FSP_SystemClockHzGet. Each bitfield in SCKDIVCR is up to 4 bits wide. */
183 #if (BSP_CFG_MCU_PART_SERIES == 8)
184 #define FSP_PRV_SCKDIVCR_DIV_MASK (0xFU)
185 #else
186 #define FSP_PRV_SCKDIVCR_DIV_MASK (0x7U)
187 #endif
188
189 /* Use the secure registers for secure projects and flat projects. */
190 #if !BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_HAS_TRUSTZONE
191 #define FSP_PRIV_TZ_USE_SECURE_REGS (1)
192 #else
193 #define FSP_PRIV_TZ_USE_SECURE_REGS (0)
194 #endif
195
196 /* Put certain BSP variables in uninitialized RAM when initializing BSP early. */
197 #if BSP_CFG_EARLY_INIT
198 #define BSP_SECTION_EARLY_INIT BSP_PLACE_IN_SECTION(BSP_SECTION_NOINIT)
199 #else
200 #define BSP_SECTION_EARLY_INIT
201 #endif
202
203 #if (BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD) && BSP_FEATURE_TZ_VERSION == 2
204 BSP_CMSE_NONSECURE_ENTRY uint8_t R_BSP_NSC_STYPE3_RegU8Read(uint8_t volatile const * p_reg);
205 BSP_CMSE_NONSECURE_ENTRY uint16_t R_BSP_NSC_STYPE3_RegU16Read(uint16_t volatile const * p_reg);
206 BSP_CMSE_NONSECURE_ENTRY uint32_t R_BSP_NSC_STYPE3_RegU32Read(uint32_t volatile const * p_reg);
207
208 #endif
209
210 #if BSP_FEATURE_TZ_HAS_TRUSTZONE && BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_VERSION == 2
211
212 /*
213 * If the STYPE3 register's security attribution is set to secure, the non-secure application must read the register
214 * from the secure application using the provided non-secure callable functions.
215 */
216 #define FSP_STYPE3_REG8_READ(X, S) (!(S) ? X : (R_BSP_NSC_STYPE3_RegU8Read((uint8_t const volatile *) &X)))
217 #define FSP_STYPE3_REG16_READ(X, S) (!(S) ? X : (R_BSP_NSC_STYPE3_RegU16Read((uint16_t const volatile *) &X)))
218 #define FSP_STYPE3_REG32_READ(X, S) (!(S) ? X : (R_BSP_NSC_STYPE3_RegU32Read((uint32_t const volatile *) &X)))
219 #elif BSP_FEATURE_TZ_HAS_TRUSTZONE && BSP_TZ_SECURE_BUILD && BSP_FEATURE_TZ_VERSION == 2
220
221 /*******************************************************************************************************************//**
222 * Read a non-secure 8-bit STYPE3 register in the secure state.
223 *
224 * @param[in] p_reg The address of the non-secure register.
225 *
226 * @return Value read from the register.
227 **********************************************************************************************************************/
R_BSP_S_STYPE3_RegU8Read(uint8_t volatile const * p_reg)228 __STATIC_INLINE uint8_t R_BSP_S_STYPE3_RegU8Read (uint8_t volatile const * p_reg)
229 {
230 p_reg = (uint8_t volatile const *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET);
231
232 return *p_reg;
233 }
234
235 /*******************************************************************************************************************//**
236 * Read a non-secure 16-bit STYPE3 register in the secure state.
237 *
238 * @param[in] p_reg The address of the non-secure register.
239 *
240 * @return Value read from the register.
241 **********************************************************************************************************************/
R_BSP_S_STYPE3_RegU16Read(uint16_t volatile const * p_reg)242 __STATIC_INLINE uint16_t R_BSP_S_STYPE3_RegU16Read (uint16_t volatile const * p_reg)
243 {
244 p_reg = (uint16_t volatile const *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET);
245
246 return *p_reg;
247 }
248
249 /*******************************************************************************************************************//**
250 * Read a non-secure 32-bit STYPE3 register in the secure state.
251 *
252 * @param[in] p_reg The address of the non-secure register.
253 *
254 * @return Value read from the register.
255 **********************************************************************************************************************/
R_BSP_S_STYPE3_RegU32Read(uint32_t volatile const * p_reg)256 __STATIC_INLINE uint32_t R_BSP_S_STYPE3_RegU32Read (uint32_t volatile const * p_reg)
257 {
258 p_reg = (uint32_t volatile const *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET);
259
260 return *p_reg;
261 }
262
263 /*
264 * If the STYPE3 register's security attribution is set to non-secure, the secure application must read the register
265 * using the non-secure aliased address.
266 */
267 #define FSP_STYPE3_REG8_READ(X, S) ((S) ? (X) : R_BSP_S_STYPE3_RegU8Read((uint8_t const volatile *) &X))
268 #define FSP_STYPE3_REG16_READ(X, S) ((S) ? (X) : R_BSP_S_STYPE3_RegU16Read((uint16_t const volatile *) &X))
269 #define FSP_STYPE3_REG32_READ(X, S) ((S) ? (X) : R_BSP_S_STYPE3_RegU32Read((uint32_t const volatile *) &X))
270 #else
271 #define FSP_STYPE3_REG8_READ(X, S) (X)
272 #define FSP_STYPE3_REG16_READ(X, S) (X)
273 #define FSP_STYPE3_REG32_READ(X, S) (X)
274 #endif
275
276 /***********************************************************************************************************************
277 * Typedef definitions
278 **********************************************************************************************************************/
279
280 /** Different warm start entry locations in the BSP. */
281 typedef enum e_bsp_warm_start_event
282 {
283 BSP_WARM_START_RESET = 0, ///< Called almost immediately after reset. No C runtime environment, clocks, or IRQs.
284 BSP_WARM_START_POST_CLOCK, ///< Called after clock initialization. No C runtime environment or IRQs.
285 BSP_WARM_START_POST_C ///< Called after clocks and C runtime environment have been set up
286 } bsp_warm_start_event_t;
287
288 /* Private enum used in R_FSP_SystemClockHzGet. Maps clock name to base bit in SCKDIVCR. */
289 typedef enum e_fsp_priv_clock
290 {
291 FSP_PRIV_CLOCK_PCLKD = 0,
292 FSP_PRIV_CLOCK_PCLKC = 4,
293 FSP_PRIV_CLOCK_PCLKB = 8,
294 FSP_PRIV_CLOCK_PCLKA = 12,
295 FSP_PRIV_CLOCK_BCLK = 16,
296 FSP_PRIV_CLOCK_PCLKE = 20,
297 FSP_PRIV_CLOCK_ICLK = 24,
298 FSP_PRIV_CLOCK_FCLK = 28,
299 FSP_PRIV_CLOCK_CPUCLK = 32,
300 } fsp_priv_clock_t;
301
302 /* Private enum used in R_FSP_SciSpiClockHzGe. Maps clock name to base bit in SCISPICKCR. */
303 typedef enum e_fsp_priv_source_clock
304 {
305 FSP_PRIV_CLOCK_HOCO = 0, ///< The high speed on chip oscillator
306 FSP_PRIV_CLOCK_MOCO = 1, ///< The middle speed on chip oscillator
307 FSP_PRIV_CLOCK_LOCO = 2, ///< The low speed on chip oscillator
308 FSP_PRIV_CLOCK_MAIN_OSC = 3, ///< The main oscillator
309 FSP_PRIV_CLOCK_SUBCLOCK = 4, ///< The subclock oscillator
310 FSP_PRIV_CLOCK_PLL = 5, ///< The PLL output
311 FSP_PRIV_CLOCK_PLL1P = 5, ///< The PLL1P output
312 FSP_PRIV_CLOCK_PLL2 = 6, ///< The PLL2 output
313 FSP_PRIV_CLOCK_PLL2P = 6, ///< The PLL2P output
314 FSP_PRIV_CLOCK_PLL1Q = 7, ///< The PLL1Q output
315 FSP_PRIV_CLOCK_PLL1R = 8, ///< The PLL1R output
316 FSP_PRIV_CLOCK_PLL2Q = 9, ///< The PLL2Q output
317 FSP_PRIV_CLOCK_PLL2R = 10, ///< The PLL2R output
318 } fsp_priv_source_clock_t;
319
320 typedef struct st_bsp_unique_id
321 {
322 union
323 {
324 uint32_t unique_id_words[4];
325 uint8_t unique_id_bytes[16];
326 };
327 } bsp_unique_id_t;
328
329 /***********************************************************************************************************************
330 * Exported global variables
331 **********************************************************************************************************************/
332 uint32_t R_BSP_SourceClockHzGet(fsp_priv_source_clock_t clock);
333
334 /***********************************************************************************************************************
335 * Global variables (defined in other files)
336 **********************************************************************************************************************/
337
338 /***********************************************************************************************************************
339 * Inline Functions
340 **********************************************************************************************************************/
341
342 /*******************************************************************************************************************//**
343 * Return active interrupt vector number value
344 *
345 * @return Active interrupt vector number value
346 **********************************************************************************************************************/
R_FSP_CurrentIrqGet(void)347 __STATIC_INLINE IRQn_Type R_FSP_CurrentIrqGet (void)
348 {
349 xPSR_Type xpsr_value;
350 xpsr_value.w = __get_xPSR();
351
352 return (IRQn_Type) (xpsr_value.b.ISR - FSP_PRIV_CORTEX_PROCESSOR_EXCEPTIONS);
353 }
354
355 /*******************************************************************************************************************//**
356 * Gets the frequency of a system clock.
357 *
358 * @return Frequency of requested clock in Hertz.
359 **********************************************************************************************************************/
R_FSP_SystemClockHzGet(fsp_priv_clock_t clock)360 __STATIC_INLINE uint32_t R_FSP_SystemClockHzGet (fsp_priv_clock_t clock)
361 {
362 #if !BSP_FEATURE_CGC_REGISTER_SET_B
363 uint32_t sckdivcr = FSP_STYPE3_REG32_READ(R_SYSTEM->SCKDIVCR, BSP_CFG_CLOCKS_SECURE);
364 uint32_t clock_div = (sckdivcr >> clock) & FSP_PRV_SCKDIVCR_DIV_MASK;
365
366 #if BSP_FEATURE_CGC_HAS_CPUCLK
367 if (FSP_PRIV_CLOCK_CPUCLK == clock)
368 {
369 return SystemCoreClock;
370 }
371
372 /* Get CPUCLK divisor */
373 uint32_t cpuclk_div = FSP_STYPE3_REG8_READ(R_SYSTEM->SCKDIVCR2, BSP_CFG_CLOCKS_SECURE) & FSP_PRV_SCKDIVCR_DIV_MASK;
374
375 /* Determine if either divisor is a multiple of 3 */
376 if ((cpuclk_div | clock_div) & 8U)
377 {
378 /* Convert divisor settings to their actual values */
379 cpuclk_div = (cpuclk_div & 8U) ? (3U << (cpuclk_div & 7U)) : (1U << cpuclk_div);
380 clock_div = (clock_div & 8U) ? (3U << (clock_div & 7U)) : (1U << clock_div);
381
382 /* Calculate clock with multiplication and division instead of shifting */
383 return (SystemCoreClock * cpuclk_div) / clock_div;
384 }
385 else
386 {
387 return (SystemCoreClock << cpuclk_div) >> clock_div;
388 }
389
390 #else
391 uint32_t iclk_div = (sckdivcr >> FSP_PRIV_CLOCK_ICLK) & FSP_PRV_SCKDIVCR_DIV_MASK;
392
393 return (SystemCoreClock << iclk_div) >> clock_div;
394 #endif
395 #else
396 FSP_PARAMETER_NOT_USED(clock);
397
398 return SystemCoreClock;
399 #endif
400 }
401
402 /*******************************************************************************************************************//**
403 * Converts a clock's CKDIVCR register value to a clock divider (Eg: SPICKDIVCR).
404 *
405 * @return Clock Divider
406 **********************************************************************************************************************/
R_FSP_ClockDividerGet(uint32_t ckdivcr)407 __STATIC_INLINE uint32_t R_FSP_ClockDividerGet (uint32_t ckdivcr)
408 {
409 if (2U >= ckdivcr)
410 {
411
412 /* clock_div:
413 * - Clock Divided by 1: 0
414 * - Clock Divided by 2: 1
415 * - Clock Divided by 4: 2
416 */
417 return 1U << ckdivcr;
418 }
419 else if (3U == ckdivcr)
420 {
421
422 /* Clock Divided by 6 */
423 return 6U;
424 }
425 else if (4U == ckdivcr)
426 {
427
428 /* Clock Divided by 8 */
429 return 8U;
430 }
431 else if (5U == ckdivcr)
432 {
433
434 /* Clock Divided by 3 */
435 return 3U;
436 }
437
438 /* Clock Divided by 5 */
439 return 5U;
440 }
441
442 #if BSP_FEATURE_BSP_HAS_SCISPI_CLOCK
443
444 /*******************************************************************************************************************//**
445 * Gets the frequency of a SCI/SPI clock.
446 *
447 * @return Frequency of requested clock in Hertz.
448 **********************************************************************************************************************/
R_FSP_SciSpiClockHzGet(void)449 __STATIC_INLINE uint32_t R_FSP_SciSpiClockHzGet (void)
450 {
451 uint32_t scispidivcr = R_SYSTEM->SCISPICKDIVCR;
452 uint32_t clock_div = R_FSP_ClockDividerGet(scispidivcr & FSP_PRV_SCKDIVCR_DIV_MASK);
453 fsp_priv_source_clock_t scispicksel = (fsp_priv_source_clock_t) R_SYSTEM->SCISPICKCR_b.SCISPICKSEL;
454
455 return R_BSP_SourceClockHzGet(scispicksel) / clock_div;
456 }
457
458 #endif
459 #if BSP_FEATURE_BSP_HAS_SPI_CLOCK
460
461 /*******************************************************************************************************************//**
462 * Gets the frequency of a SPI clock.
463 *
464 * @return Frequency of requested clock in Hertz.
465 **********************************************************************************************************************/
R_FSP_SpiClockHzGet(void)466 __STATIC_INLINE uint32_t R_FSP_SpiClockHzGet (void)
467 {
468 uint32_t spidivcr = FSP_STYPE3_REG8_READ(R_SYSTEM->SPICKDIVCR, BSP_CFG_CLOCKS_SECURE);
469 uint32_t clock_div = R_FSP_ClockDividerGet(spidivcr & FSP_PRV_SCKDIVCR_DIV_MASK);
470 fsp_priv_source_clock_t spicksel =
471 (fsp_priv_source_clock_t) ((FSP_STYPE3_REG8_READ(R_SYSTEM->SPICKCR,
472 BSP_CFG_CLOCKS_SECURE) & R_SYSTEM_SPICKCR_CKSEL_Msk) >>
473 R_SYSTEM_SPICKCR_CKSEL_Pos);
474
475 return R_BSP_SourceClockHzGet(spicksel) / clock_div;
476 }
477
478 #endif
479 #if BSP_FEATURE_BSP_HAS_SCI_CLOCK
480
481 /*******************************************************************************************************************//**
482 * Gets the frequency of a SCI clock.
483 *
484 * @return Frequency of requested clock in Hertz.
485 **********************************************************************************************************************/
R_FSP_SciClockHzGet(void)486 __STATIC_INLINE uint32_t R_FSP_SciClockHzGet (void)
487 {
488 uint32_t scidivcr = FSP_STYPE3_REG8_READ(R_SYSTEM->SCICKDIVCR, BSP_CFG_CLOCKS_SECURE);
489 uint32_t clock_div = R_FSP_ClockDividerGet(scidivcr & FSP_PRV_SCKDIVCR_DIV_MASK);
490 fsp_priv_source_clock_t scicksel =
491 (fsp_priv_source_clock_t) (FSP_STYPE3_REG8_READ(R_SYSTEM->SCICKCR,
492 BSP_CFG_CLOCKS_SECURE) & R_SYSTEM_SCICKCR_SCICKSEL_Msk >>
493 R_SYSTEM_SCICKCR_SCICKSEL_Pos);
494
495 return R_BSP_SourceClockHzGet(scicksel) / clock_div;
496 }
497
498 #endif
499
500 /*******************************************************************************************************************//**
501 * Get unique ID for this device.
502 *
503 * @return A pointer to the unique identifier structure
504 **********************************************************************************************************************/
R_BSP_UniqueIdGet(void)505 __STATIC_INLINE bsp_unique_id_t const * R_BSP_UniqueIdGet (void)
506 {
507 #if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_NONSECURE_BUILD == 1
508
509 return (bsp_unique_id_t *) (BSP_FEATURE_BSP_UNIQUE_ID_POINTER | BSP_FEATURE_TZ_NS_OFFSET);
510 #else
511
512 return (bsp_unique_id_t *) BSP_FEATURE_BSP_UNIQUE_ID_POINTER;
513 #endif
514 }
515
516 /*******************************************************************************************************************//**
517 * Disables the flash cache.
518 **********************************************************************************************************************/
R_BSP_FlashCacheDisable(void)519 __STATIC_INLINE void R_BSP_FlashCacheDisable (void)
520 {
521 #if BSP_FEATURE_BSP_FLASH_CACHE
522 R_FCACHE->FCACHEE = 0U;
523 #endif
524
525 #if BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE
526
527 /* Disable the C-Cache. */
528 R_CACHE->CCACTL = 0U;
529 #endif
530 }
531
532 /*******************************************************************************************************************//**
533 * Enables the flash cache.
534 **********************************************************************************************************************/
R_BSP_FlashCacheEnable(void)535 __STATIC_INLINE void R_BSP_FlashCacheEnable (void)
536 {
537 #if BSP_FEATURE_BSP_FLASH_CACHE
538
539 /* Invalidate the flash cache and wait until it is invalidated. (See section 55.3.2.2 "Operation" of the Flash Cache
540 * in the RA6M3 manual R01UH0878EJ0100). */
541 R_FCACHE->FCACHEIV = 1U;
542 FSP_HARDWARE_REGISTER_WAIT(R_FCACHE->FCACHEIV, 0U);
543
544 /* Enable flash cache. */
545 R_FCACHE->FCACHEE = 1U;
546 #endif
547
548 #if BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE
549
550 /* Configure the C-Cache line size. */
551 R_CACHE->CCALCF = BSP_CFG_C_CACHE_LINE_SIZE;
552
553 /* Enable the C-Cache. */
554 R_CACHE->CCACTL = 1U;
555 #endif
556 }
557
558 /***********************************************************************************************************************
559 * Exported global functions (to be accessed by other files)
560 **********************************************************************************************************************/
561 #if ((1 == BSP_CFG_ERROR_LOG) || (1 == BSP_CFG_ASSERT))
562
563 /** Prototype of default function called before errors are returned in FSP code if BSP_CFG_LOG_ERRORS is set to 1. */
564 void fsp_error_log(fsp_err_t err, const char * file, int32_t line);
565
566 #endif
567
568 /** In the event of an unrecoverable error the BSP will by default call the __BKPT() intrinsic function which will
569 * alert the user of the error. The user can override this default behavior by defining their own
570 * BSP_CFG_HANDLE_UNRECOVERABLE_ERROR macro.
571 */
572 #if !defined(BSP_CFG_HANDLE_UNRECOVERABLE_ERROR)
573
574 #define BSP_CFG_HANDLE_UNRECOVERABLE_ERROR(x) __BKPT((x))
575 #endif
576
577 /** @} (end addtogroup BSP_MCU) */
578
579 /** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
580 FSP_FOOTER
581
582 #endif
583
