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Searched refs:sysclk (Results 1 – 25 of 54) sorted by relevance

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/Zephyr-latest/boards/arm/mps3/
Dmps3_common_soc_peripheral.dtsi8 sysclk: system-clock { label
75 clocks = <&sysclk>;
85 clocks = <&sysclk>;
95 clocks = <&sysclk>;
156 clocks = <&sysclk>;
165 clocks = <&sysclk>;
174 clocks = <&sysclk>;
183 clocks = <&sysclk>;
192 clocks = <&sysclk>;
202 clocks = <&sysclk>;
/Zephyr-latest/dts/arm/aspeed/
Dast10x0.dtsi31 sysclk: sysclk { label
46 clocks = <&sysclk ASPEED_CLK_UART5>;
/Zephyr-latest/tests/cmake/hwm/board_extend/oot_root/boards/arm/mps2/
Dmps2_an521-common.dtsi7 sysclk: system-clock { label
78 clocks = <&sysclk>;
86 clocks = <&sysclk>;
95 clocks = <&sysclk>;
104 clocks = <&sysclk>;
113 clocks = <&sysclk>;
122 clocks = <&sysclk>;
/Zephyr-latest/boards/arm/mps2/
Dmps2_an521-common.dtsi7 sysclk: system-clock { label
78 clocks = <&sysclk>;
86 clocks = <&sysclk>;
95 clocks = <&sysclk>;
104 clocks = <&sysclk>;
113 clocks = <&sysclk>;
122 clocks = <&sysclk>;
Dmps2_an385.dts103 sysclk: system-clock { label
133 clocks = <&sysclk>;
142 clocks = <&sysclk>;
151 clocks = <&sysclk>;
160 clocks = <&sysclk>;
166 clocks = <&sysclk>;
175 clocks = <&sysclk>;
/Zephyr-latest/dts/arm/ti/
Dmsp432p4xx.dtsi24 sysclk: system-clock { label
35 clocks = <&sysclk>;
Dlm3s6965.dtsi22 sysclk: system-clock { label
45 clocks = <&sysclk>;
53 clocks = <&sysclk>;
61 clocks = <&sysclk>;
Dcc32xx.dtsi53 sysclk: system-clock { label
64 clocks = <&sysclk>;
72 clocks = <&sysclk>;
78 clocks = <&sysclk>;
Dcc13xx_cc26xx.dtsi57 sysclk: system-clock { label
159 clocks = <&sysclk>;
167 clocks = <&sysclk>;
/Zephyr-latest/boards/arm/v2m_beetle/
Dv2m_beetle.dts43 sysclk: system-clock { label
75 clocks = <&sysclk &syscon>;
83 clocks = <&sysclk &syscon>;
89 clocks = <&sysclk>;
/Zephyr-latest/boards/arm/v2m_musca_b1/
Dv2m_musca_b1-common.dtsi30 clocks = <&sysclk>;
39 clocks = <&sysclk>;
Dv2m_musca_b1_musca_b1_ns.dts54 sysclk: system-clock { label
/Zephyr-latest/boards/arm/v2m_musca_s1/
Dv2m_musca_s1-common.dtsi30 clocks = <&sysclk>;
39 clocks = <&sysclk>;
Dv2m_musca_s1_musca_s1_ns.dts54 sysclk: system-clock { label
/Zephyr-latest/dts/arm/infineon/cat3/xmc/
Dxmc4xxx.dtsi35 sysclk: system-clock { label
119 clocks = <&sysclk>;
125 clocks = <&sysclk>;
131 clocks = <&sysclk>;
137 clocks = <&sysclk>;
143 clocks = <&sysclk>;
149 clocks = <&sysclk>;
/Zephyr-latest/drivers/clock_control/
Dclock_stm32_ll_h7.c221 uint32_t sysclk = 0; in get_hclk_frequency() local
226 sysclk = STM32_HSI_FREQ/STM32_HSI_DIVISOR; in get_hclk_frequency()
229 sysclk = STM32_CSI_FREQ; in get_hclk_frequency()
232 sysclk = STM32_HSE_FREQ; in get_hclk_frequency()
236 sysclk = get_pllout_frequency(get_pllsrc_frequency(), in get_hclk_frequency()
244 return get_bus_clock(sysclk, STM32_HPRE); in get_hclk_frequency()
994 uint32_t sysclk, hsivalue, pllsource, pllm, pllp, core_presc; local
1000 sysclk = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)
1005 sysclk = CSI_VALUE;
1009 sysclk = HSE_VALUE;
[all …]
Dclock_stm32_ll_wb0.c275 uint32_t *rate, uint32_t slow_clock, uint32_t sysclk, uint32_t clk_sys) in get_apb0_periph_clkrate() argument
297 *rate = sysclk; in get_apb0_periph_clkrate()
407 uint32_t sysclk, slow_clock, clk_sys; in stm32_clock_control_get_subsys_rate() local
426 sysclk = STM32_HSE_FREQ; in stm32_clock_control_get_subsys_rate()
428 sysclk = STM32_HSI_FREQ; in stm32_clock_control_get_subsys_rate()
469 sysclk, clk_sys); in stm32_clock_control_get_subsys_rate()
473 *rate = sysclk; in stm32_clock_control_get_subsys_rate()
Dclock_control_wch_rcc.c67 uint32_t sysclk = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC; in clock_control_wch_rcc_get_rate() local
68 uint32_t ahbclk = sysclk; in clock_control_wch_rcc_get_rate()
/Zephyr-latest/tests/drivers/build_all/watchdog/boards/
Dqemu_cortex_m3.overlay11 clocks = <&sysclk>;
/Zephyr-latest/dts/arc/synopsys/
Demsk.dtsi43 sysclk: system-clock { label
148 clocks = <&sysclk>;
160 clocks = <&sysclk>;
Darc_iot.dtsi62 sysclk: system-clock { label
237 clocks = <&sysclk>;
250 clocks = <&sysclk>;
263 clocks = <&sysclk>;
/Zephyr-latest/soc/intel/intel_adsp/common/
Dclk.c125 [ADSP_CLOCK_SOURCE_XTAL_OSC] = { DT_PROP(DT_NODELABEL(sysclk), clock_frequency) },
140 [ADSP_CLOCK_SOURCE_WOV_RING_OSC] = { DT_PROP(DT_NODELABEL(sysclk), clock_frequency) },
/Zephyr-latest/drivers/audio/
Dwm8904.c310 static void wm8904_set_master_clock(const struct device *dev, audio_dai_cfg_t *cfg, uint32_t sysclk) in wm8904_set_master_clock() argument
320 sysclk = sysclk >> (sysclkDiv & 0x1U); in wm8904_set_master_clock()
321 LOG_DBG("Codec sysclk: %d", sysclk); in wm8904_set_master_clock()
323 if ((sysclk / bclk > 48U) || (bclk / sampleRate > 2047U) || (bclk / sampleRate < 8U)) { in wm8904_set_master_clock()
331 bclkDiv = (sysclk * 10U) / bclk; in wm8904_set_master_clock()
/Zephyr-latest/modules/hal_silabs/simplicity_sdk/config/
Dsl_clock_manager_tree_config.h26 (DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(sysclk)), DT_NODELABEL(fsrco)) \
28 : DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(sysclk)), DT_NODELABEL(hfrcodpll)) \
30 : DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(sysclk)), DT_NODELABEL(hfxo)) \
32 : DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(sysclk)), DT_NODELABEL(clkin0)) \
54 (DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(traceclk)), DT_NODELABEL(sysclk)) \
/Zephyr-latest/dts/arm/silabs/
Defr32bg2x.dtsi21 sysclk: sysclk { label
29 clocks = <&sysclk>;
57 clocks = <&sysclk>;

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