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Searched refs:vaddr (Results 1 – 25 of 39) sorted by relevance

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/hal_espressif-latest/components/soc/esp32s2/include/soc/
Dext_mem_defs.h46 #define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name… argument
48 #define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr) argument
49 #define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr) argument
50 #define ADDRESS_IN_IRAM1(vaddr) ADDRESS_IN_BUS(IRAM1, vaddr) argument
51 #define ADDRESS_IN_DROM0(vaddr) ADDRESS_IN_BUS(DROM0, vaddr) argument
52 #define ADDRESS_IN_DRAM0(vaddr) ADDRESS_IN_BUS(DRAM0, vaddr) argument
53 #define ADDRESS_IN_DRAM0_CACHE(vaddr) ADDRESS_IN_BUS(DRAM0_CACHE, vaddr) argument
54 #define ADDRESS_IN_DRAM1(vaddr) ADDRESS_IN_BUS(DRAM1, vaddr) argument
55 #define ADDRESS_IN_DPORT(vaddr) ADDRESS_IN_BUS(DPORT, vaddr) argument
56 #define ADDRESS_IN_DPORT_CACHE(vaddr) ADDRESS_IN_BUS(DPORT_CACHE, vaddr) argument
/hal_espressif-latest/components/soc/esp32/include/soc/
Dext_mem_defs.h33 #define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name… argument
34 #define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr) argument
35 #define ADDRESS_IN_IRAM1_CACHE(vaddr) ADDRESS_IN_BUS(IRAM1_CACHE, vaddr) argument
36 #define ADDRESS_IN_IROM0_CACHE(vaddr) ADDRESS_IN_BUS(IROM0_CACHE, vaddr) argument
37 #define ADDRESS_IN_DRAM1_CACHE(vaddr) ADDRESS_IN_BUS(DRAM1_CACHE, vaddr) argument
38 #define ADDRESS_IN_DROM0_CACHE(vaddr) ADDRESS_IN_BUS(DROM0_CACHE, vaddr) argument
/hal_espressif-latest/components/soc/esp32c3/include/soc/
Dext_mem_defs.h29 #define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name… argument
31 #define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr) argument
32 #define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr) argument
33 #define ADDRESS_IN_DRAM0(vaddr) ADDRESS_IN_BUS(DRAM0, vaddr) argument
34 #define ADDRESS_IN_DRAM0_CACHE(vaddr) ADDRESS_IN_BUS(DRAM0_CACHE, vaddr) argument
/hal_espressif-latest/components/esp_hw_support/port/esp32/
Dcache_sram_mmu.c45 unsigned int cache_sram_mmu_set_rom(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, in…
56 unsigned int IRAM_ATTR cache_sram_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int pad… in cache_sram_mmu_set() argument
61 return cache_sram_mmu_set_rom(cpu_no, pid, vaddr, paddr, psize, num); in cache_sram_mmu_set()
68 if( (ADDRESS_CHECK(vaddr,psize)) || (ADDRESS_CHECK(paddr,psize)) ){ in cache_sram_mmu_set()
94 if(vaddr >= PRO_DRAM1_START_ADDR && vaddr < PRO_DRAM1_END_ADDR(psize)){ in cache_sram_mmu_set()
95 mmu_addr = 1152 + ((vaddr & (0x3FFFFF >> mask_s)) >> shift); in cache_sram_mmu_set()
100 if(vaddr >= PRO_DRAM1_START_ADDR && vaddr < PRO_DRAM1_END_ADDR(psize)){ in cache_sram_mmu_set()
101 mmu_addr = (1024 + (pid<<7)) + ((vaddr & (0x3FFFFF >> mask_s)) >> shift); in cache_sram_mmu_set()
132 unsigned int cache_sram_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int ps… in cache_sram_mmu_set() argument
133 return cache_sram_mmu_set_rom(cpu_no, pid, vaddr, paddr, psize, num); in cache_sram_mmu_set()
/hal_espressif-latest/components/soc/esp32c6/include/soc/
Dext_mem_defs.h31 #define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name… argument
33 #define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr) argument
34 #define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr) argument
35 #define ADDRESS_IN_DRAM0(vaddr) ADDRESS_IN_BUS(DRAM0, vaddr) argument
36 #define ADDRESS_IN_DRAM0_CACHE(vaddr) ADDRESS_IN_BUS(DRAM0_CACHE, vaddr) argument
/hal_espressif-latest/components/soc/esp32s3/include/soc/
Dext_mem_defs.h28 #define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name… argument
30 #define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr) argument
31 #define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr) argument
32 #define ADDRESS_IN_DRAM0(vaddr) ADDRESS_IN_BUS(DRAM0, vaddr) argument
33 #define ADDRESS_IN_DRAM0_CACHE(vaddr) ADDRESS_IN_BUS(DRAM0_CACHE, vaddr) argument
/hal_espressif-latest/components/soc/esp32h2/include/soc/
Dext_mem_defs.h31 #define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name… argument
33 #define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr) argument
34 #define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr) argument
35 #define ADDRESS_IN_DRAM0(vaddr) ADDRESS_IN_BUS(DRAM0, vaddr) argument
36 #define ADDRESS_IN_DRAM0_CACHE(vaddr) ADDRESS_IN_BUS(DRAM0_CACHE, vaddr) argument
/hal_espressif-latest/components/soc/esp32c2/include/soc/
Dext_mem_defs.h39 #define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name… argument
41 #define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr) argument
42 #define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr) argument
43 #define ADDRESS_IN_DRAM0(vaddr) ADDRESS_IN_BUS(DRAM0, vaddr) argument
44 #define ADDRESS_IN_DRAM0_CACHE(vaddr) ADDRESS_IN_BUS(DRAM0_CACHE, vaddr) argument
/hal_espressif-latest/components/esp_system/port/arch/xtensa/
Dpanic_arch.c174 uint32_t vaddr = 0, size = 0; in print_cache_err_details() local
181 vaddr = REG_READ(EXTMEM_PRO_ICACHE_MEM_SYNC0_REG); in print_cache_err_details()
184 panic_print_hex(vaddr); in print_cache_err_details()
190 vaddr = REG_READ(EXTMEM_PRO_ICACHE_PRELOAD_ADDR_REG); in print_cache_err_details()
193 panic_print_hex(vaddr); in print_cache_err_details()
199 vaddr = REG_READ(EXTMEM_PRO_ICACHE_REJECT_VADDR_REG); in print_cache_err_details()
201 panic_print_hex(vaddr); in print_cache_err_details()
213 vaddr = REG_READ(EXTMEM_PRO_DCACHE_MEM_SYNC0_REG); in print_cache_err_details()
216 panic_print_hex(vaddr); in print_cache_err_details()
222 vaddr = REG_READ(EXTMEM_PRO_DCACHE_PRELOAD_ADDR_REG); in print_cache_err_details()
[all …]
/hal_espressif-latest/components/hal/
Dmmu_hal.c75 void mmu_hal_map_region(uint32_t mmu_id, mmu_target_t mem_type, uint32_t vaddr, uint32_t paddr, uin… in mmu_hal_map_region() argument
78 HAL_ASSERT(vaddr % page_size_in_bytes == 0); in mmu_hal_map_region()
81 …HAL_ASSERT(mmu_hal_check_valid_ext_vaddr_region(mmu_id, vaddr, len, MMU_VADDR_DATA | MMU_VADDR_INS… in mmu_hal_map_region()
91 entry_id = mmu_ll_get_entry_id(mmu_id, vaddr); in mmu_hal_map_region()
93 vaddr += page_size_in_bytes; in mmu_hal_map_region()
99 void mmu_hal_unmap_region(uint32_t mmu_id, uint32_t vaddr, uint32_t len) in mmu_hal_unmap_region() argument
102 HAL_ASSERT(vaddr % page_size_in_bytes == 0); in mmu_hal_unmap_region()
103 …HAL_ASSERT(mmu_hal_check_valid_ext_vaddr_region(mmu_id, vaddr, len, MMU_VADDR_DATA | MMU_VADDR_INS… in mmu_hal_unmap_region()
108 entry_id = mmu_ll_get_entry_id(mmu_id, vaddr); in mmu_hal_unmap_region()
110 vaddr += page_size_in_bytes; in mmu_hal_unmap_region()
[all …]
Dcache_hal.c168 void cache_hal_invalidate_addr(uint32_t vaddr, uint32_t size) in cache_hal_invalidate_addr() argument
171 …HAL_ASSERT(mmu_hal_check_valid_ext_vaddr_region(0, vaddr, size, MMU_VADDR_DATA | MMU_VADDR_INSTRUC… in cache_hal_invalidate_addr()
172 Cache_Invalidate_Addr(vaddr, size); in cache_hal_invalidate_addr()
176 void cache_hal_writeback_addr(uint32_t vaddr, uint32_t size) in cache_hal_writeback_addr() argument
178 HAL_ASSERT(mmu_hal_check_valid_ext_vaddr_region(0, vaddr, size, MMU_VADDR_DATA)); in cache_hal_writeback_addr()
179 Cache_WriteBack_Addr(vaddr, size); in cache_hal_writeback_addr()
/hal_espressif-latest/components/hal/esp32s2/include/hal/
Dmmu_ll.h29 static inline uint32_t mmu_ll_vaddr_to_laddr(uint32_t vaddr) in mmu_ll_vaddr_to_laddr() argument
31 return vaddr & SOC_MMU_LINEAR_ADDR_MASK; in mmu_ll_vaddr_to_laddr()
139 static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr) in mmu_ll_get_entry_id() argument
144 if (ADDRESS_IN_DROM0(vaddr)) { in mmu_ll_get_entry_id()
146 } else if (ADDRESS_IN_IRAM0_CACHE(vaddr)) { in mmu_ll_get_entry_id()
148 } else if (ADDRESS_IN_IRAM1(vaddr)) { in mmu_ll_get_entry_id()
150 } else if (ADDRESS_IN_DPORT_CACHE(vaddr)) { in mmu_ll_get_entry_id()
152 } else if (ADDRESS_IN_DRAM1(vaddr)) { in mmu_ll_get_entry_id()
154 } else if (ADDRESS_IN_DRAM0_CACHE(vaddr)) { in mmu_ll_get_entry_id()
160 return offset + ((vaddr & MMU_VADDR_MASK) >> 16); in mmu_ll_get_entry_id()
/hal_espressif-latest/components/esp_rom/include/esp32/rom/
Dcache.h68 …igned int IRAM_ATTR cache_flash_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int padd… in cache_flash_mmu_set() argument
70 …extern unsigned int cache_flash_mmu_set_rom(int cpu_no, int pid, unsigned int vaddr, unsigned int … in cache_flash_mmu_set()
75 ret = cache_flash_mmu_set_rom(cpu_no, pid, vaddr, paddr, psize, num); in cache_flash_mmu_set()
111 unsigned int IRAM_ATTR cache_sram_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int pad…
/hal_espressif-latest/components/hal/esp32/include/hal/
Dmmu_ll.h31 static inline uint32_t mmu_ll_vaddr_to_laddr(uint32_t vaddr) in mmu_ll_vaddr_to_laddr() argument
33 return vaddr & SOC_MMU_LINEAR_ADDR_MASK; in mmu_ll_vaddr_to_laddr()
144 static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr) in mmu_ll_get_entry_id() argument
152 if (ADDRESS_IN_DROM0_CACHE(vaddr)) { in mmu_ll_get_entry_id()
156 } else if (ADDRESS_IN_IRAM0_CACHE(vaddr)) { in mmu_ll_get_entry_id()
160 } else if (ADDRESS_IN_IRAM1_CACHE(vaddr)) { in mmu_ll_get_entry_id()
164 } else if (ADDRESS_IN_IROM0_CACHE(vaddr)) { in mmu_ll_get_entry_id()
168 } else if (ADDRESS_IN_DRAM1_CACHE(vaddr)) { in mmu_ll_get_entry_id()
177 return offset + ((vaddr & vaddr_mask) >> shift_code); in mmu_ll_get_entry_id()
/hal_espressif-latest/components/hal/include/hal/
Dmmu_hal.h64 void mmu_hal_map_region(uint32_t mmu_id, mmu_target_t mem_type, uint32_t vaddr, uint32_t paddr, uin…
73 void mmu_hal_unmap_region(uint32_t mmu_id, uint32_t vaddr, uint32_t len);
87 bool mmu_hal_vaddr_to_paddr(uint32_t mmu_id, uint32_t vaddr, uint32_t *out_paddr, mmu_target_t *out…
Dcache_hal.h80 void cache_hal_invalidate_addr(uint32_t vaddr, uint32_t size);
91 void cache_hal_writeback_addr(uint32_t vaddr, uint32_t size);
/hal_espressif-latest/components/esp_mm/
Desp_cache.c66 uint32_t vaddr = (uint32_t)addr; in esp_cache_msync() local
71 cache_hal_writeback_addr(vaddr, size); in esp_cache_msync()
73 cache_hal_invalidate_addr(vaddr, size); in esp_cache_msync()
Desp_mmu_map.c318 uint32_t vaddr = 0; in esp_mmu_map_reserve_block_with_caps() local
320 vaddr = mmu_ll_laddr_to_vaddr(laddr, MMU_VADDR_INSTRUCTION); in esp_mmu_map_reserve_block_with_caps()
322 vaddr = mmu_ll_laddr_to_vaddr(laddr, MMU_VADDR_DATA); in esp_mmu_map_reserve_block_with_caps()
324 *out_ptr = (void *)vaddr; in esp_mmu_map_reserve_block_with_caps()
702 static bool NOINLINE_ATTR IRAM_ATTR s_vaddr_to_paddr(uint32_t vaddr, esp_paddr_t *out_paddr, mmu_ta… in s_vaddr_to_paddr() argument
707 bool is_mapped = mmu_hal_vaddr_to_paddr(0, vaddr, out_paddr, out_target); in s_vaddr_to_paddr()
713 esp_err_t esp_mmu_vaddr_to_paddr(void *vaddr, esp_paddr_t *out_paddr, mmu_target_t *out_target) in esp_mmu_vaddr_to_paddr() argument
715 ESP_RETURN_ON_FALSE(vaddr && out_paddr, ESP_ERR_INVALID_ARG, TAG, "null pointer"); in esp_mmu_vaddr_to_paddr()
716 …ESP_RETURN_ON_FALSE(mmu_hal_check_valid_ext_vaddr_region(0, (uint32_t)vaddr, 1, MMU_VADDR_DATA | M… in esp_mmu_vaddr_to_paddr()
721 bool is_mapped = s_vaddr_to_paddr((uint32_t)vaddr, &paddr, &target); in esp_mmu_vaddr_to_paddr()
[all …]
/hal_espressif-latest/components/spi_flash/
Dflash_mmap.c321 uint32_t vaddr = 0; in is_page_mapped_in_cache() local
323 mmu_hal_paddr_to_vaddr(0, phys_addr, MMU_TARGET_FLASH0, MMU_VADDR_INSTRUCTION, &vaddr); in is_page_mapped_in_cache()
325 mmu_hal_paddr_to_vaddr(0, phys_addr, MMU_TARGET_FLASH0, MMU_VADDR_DATA, &vaddr); in is_page_mapped_in_cache()
327 *out_ptr = (void *)vaddr; in is_page_mapped_in_cache()
347 const void *vaddr = NULL; in spi_flash_check_and_flush_cache() local
348 if (is_page_mapped_in_cache(addr, &vaddr)) { in spi_flash_check_and_flush_cache()
353 if (vaddr != NULL) { in spi_flash_check_and_flush_cache()
354 cache_hal_invalidate_addr((uint32_t)vaddr, SPI_FLASH_MMU_PAGE_SIZE); in spi_flash_check_and_flush_cache()
/hal_espressif-latest/components/hal/esp32s3/include/hal/
Dmmu_ll.h29 static inline uint32_t mmu_ll_vaddr_to_laddr(uint32_t vaddr) in mmu_ll_vaddr_to_laddr() argument
31 return vaddr & SOC_MMU_LINEAR_ADDR_MASK; in mmu_ll_vaddr_to_laddr()
139 static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr) in mmu_ll_get_entry_id() argument
142 return ((vaddr & MMU_VADDR_MASK) >> 16); in mmu_ll_get_entry_id()
/hal_espressif-latest/components/hal/esp32c3/include/hal/
Dmmu_ll.h29 static inline uint32_t mmu_ll_vaddr_to_laddr(uint32_t vaddr) in mmu_ll_vaddr_to_laddr() argument
31 return vaddr & SOC_MMU_LINEAR_ADDR_MASK; in mmu_ll_vaddr_to_laddr()
139 static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr) in mmu_ll_get_entry_id() argument
142 return ((vaddr & MMU_VADDR_MASK) >> 16); in mmu_ll_get_entry_id()
/hal_espressif-latest/components/esp_rom/include/esp32c6/rom/
Dcache.h205 int Cache_MSPI_MMU_Set(uint32_t sensitive, uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint3…
233 int Cache_Dbus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint32_t psize, uint32_t n…
604 #define Cache_Dbus_MMU_Set(ext_ram, vaddr, paddr, psize, num, fixed) \ argument
605 …Cache_MSPI_MMU_Set(ets_efuse_cache_encryption_enabled() ? MMU_SENSITIVE : 0, ext_ram, vaddr, paddr…
/hal_espressif-latest/components/esp_rom/include/esp32h2/rom/
Dcache.h209 int Cache_MSPI_MMU_Set(uint32_t sensitive, uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint3…
237 int Cache_Dbus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint32_t psize, uint32_t n…
607 #define Cache_Dbus_MMU_Set(ext_ram, vaddr, paddr, psize, num, fixed) \ argument
608 …Cache_MSPI_MMU_Set(ets_efuse_cache_encryption_enabled() ? MMU_SENSITIVE : 0, ext_ram, vaddr, paddr…
/hal_espressif-latest/components/hal/esp32c2/include/hal/
Dmmu_ll.h29 static inline uint32_t mmu_ll_vaddr_to_laddr(uint32_t vaddr) in mmu_ll_vaddr_to_laddr() argument
31 return vaddr & SOC_MMU_LINEAR_ADDR_MASK; in mmu_ll_vaddr_to_laddr()
138 static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr) in mmu_ll_get_entry_id() argument
158 return ((vaddr & MMU_VADDR_MASK) >> shift_code); in mmu_ll_get_entry_id()
/hal_espressif-latest/components/hal/esp32c6/include/hal/
Dmmu_ll.h29 static inline uint32_t mmu_ll_vaddr_to_laddr(uint32_t vaddr) in mmu_ll_vaddr_to_laddr() argument
31 return vaddr & SOC_MMU_LINEAR_ADDR_MASK; in mmu_ll_vaddr_to_laddr()
137 static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr) in mmu_ll_get_entry_id() argument
158 return ((vaddr & MMU_VADDR_MASK) >> shift_code); in mmu_ll_get_entry_id()

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