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Searched refs:REG_CLR_BIT (Results 1 – 25 of 106) sorted by relevance

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/hal_espressif-latest/components/bootloader_support/src/esp32c3/
Dbootloader_soc.c12 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST); in bootloader_ana_super_wdt_reset_config()
15 REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); in bootloader_ana_super_wdt_reset_config()
23 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOD_RST); in bootloader_ana_bod_reset_config()
28 REG_CLR_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN); in bootloader_ana_bod_reset_config()
34 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_GLITCH_RST); in bootloader_ana_clock_glitch_reset_config()
39 REG_CLR_BIT(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_GLITCH_RST_EN); in bootloader_ana_clock_glitch_reset_config()
/hal_espressif-latest/components/bootloader_support/src/esp32s3/
Dbootloader_soc.c12 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST); in bootloader_ana_super_wdt_reset_config()
15 REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); in bootloader_ana_super_wdt_reset_config()
23 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOD_RST); in bootloader_ana_bod_reset_config()
28 REG_CLR_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN); in bootloader_ana_bod_reset_config()
34 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_GLITCH_RST); in bootloader_ana_clock_glitch_reset_config()
39 REG_CLR_BIT(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_GLITCH_RST_EN); in bootloader_ana_clock_glitch_reset_config()
/hal_espressif-latest/zephyr/esp32c3/src/
Dsoc_init.c31 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST); in ana_super_wdt_reset_config()
34 REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); in ana_super_wdt_reset_config()
42 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOD_RST); in ana_bod_reset_config()
47 REG_CLR_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN); in ana_bod_reset_config()
53 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_GLITCH_RST); in ana_clock_glitch_reset_config()
58 REG_CLR_BIT(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_GLITCH_RST_EN); in ana_clock_glitch_reset_config()
102 REG_CLR_BIT(SYSTEM_CPU_PERI_RST_EN_REG, SYSTEM_RST_EN_ASSIST_DEBUG); in wdt_reset_cpu0_info_enable()
/hal_espressif-latest/zephyr/esp32c2/src/
Dsoc_init.c21 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST); in ana_super_wdt_reset_config()
24 REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); in ana_super_wdt_reset_config()
32 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOD_RST); in ana_bod_reset_config()
37 REG_CLR_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN); in ana_bod_reset_config()
57 REG_CLR_BIT(SYSTEM_CPU_PERI_RST_EN_REG, SYSTEM_RST_EN_ASSIST_DEBUG); in wdt_reset_cpu0_info_enable()
/hal_espressif-latest/components/bootloader_support/src/esp32c2/
Dbootloader_soc.c12 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST); in bootloader_ana_super_wdt_reset_config()
15 REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); in bootloader_ana_super_wdt_reset_config()
23 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOD_RST); in bootloader_ana_bod_reset_config()
28 REG_CLR_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN); in bootloader_ana_bod_reset_config()
/hal_espressif-latest/zephyr/esp32s3/src/
Dsoc_init.c20 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST); in ana_super_wdt_reset_config()
23 REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); in ana_super_wdt_reset_config()
31 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOD_RST); in ana_bod_reset_config()
36 REG_CLR_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN); in ana_bod_reset_config()
42 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_GLITCH_RST); in ana_clock_glitch_reset_config()
47 REG_CLR_BIT(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_GLITCH_RST_EN); in ana_clock_glitch_reset_config()
101 REG_CLR_BIT(SYSTEM_CPU_PERI_RST_EN_REG, SYSTEM_RST_EN_ASSIST_DEBUG); in wdt_reset_cpu0_info_enable()
/hal_espressif-latest/components/bootloader_support/src/esp32h2/
Dbootloader_soc.c13 REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST); in bootloader_ana_super_wdt_reset_config()
18 REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_BOD_RST); in bootloader_ana_bod_reset_config()
23 … REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_BOD_MODE1_CNTL_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA); in bootloader_ana_bod_reset_config()
/hal_espressif-latest/components/bootloader_support/src/esp32c6/
Dbootloader_soc.c15 REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST); in bootloader_ana_super_wdt_reset_config()
20 REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_BOD_RST); in bootloader_ana_bod_reset_config()
25 … REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_BOD_MODE1_CNTL_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA); in bootloader_ana_bod_reset_config()
/hal_espressif-latest/zephyr/esp32c6/src/
Dsoc_init.c45 REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST); in ana_super_wdt_reset_config()
50 REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_BOD_RST); in ana_bod_reset_config()
56 REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_BOD_MODE1_CNTL_REG, in ana_bod_reset_config()
78 REG_CLR_BIT(PCR_ASSIST_CONF_REG, PCR_ASSIST_RST_EN); in wdt_reset_cpu0_info_enable()
/hal_espressif-latest/components/esp_hw_support/port/esp32s3/
Drtc_init.c172 REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_FORCE_PU); in rtc_init()
173 … REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_WRAP_FORCE_NOISO | RTC_CNTL_DG_WRAP_FORCE_ISO); in rtc_init()
175 REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_NOISO | RTC_CNTL_WIFI_FORCE_ISO); in rtc_init()
176 REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PU); in rtc_init()
178 REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_BT_FORCE_NOISO | RTC_CNTL_BT_FORCE_ISO); in rtc_init()
179 REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_FORCE_PU); in rtc_init()
181 … REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CPU_TOP_FORCE_NOISO | RTC_CNTL_CPU_TOP_FORCE_ISO); in rtc_init()
182 REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_TOP_FORCE_PU); in rtc_init()
184 … REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PERI_FORCE_NOISO | RTC_CNTL_DG_PERI_FORCE_ISO); in rtc_init()
185 REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_PERI_FORCE_PU); in rtc_init()
[all …]
Drtc_sleep.c181 REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_NOISO); in rtc_sleep_init()
182 REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PU); in rtc_sleep_init()
189 … REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CPU_TOP_FORCE_NOISO | RTC_CNTL_CPU_TOP_FORCE_ISO); in rtc_sleep_init()
190 REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_TOP_FORCE_PU); in rtc_sleep_init()
197 … REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PERI_FORCE_NOISO | RTC_CNTL_DG_PERI_FORCE_ISO); in rtc_sleep_init()
198 REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_PERI_FORCE_PU); in rtc_sleep_init()
205 … REG_CLR_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_FORCE_NOISO | RTC_CNTL_FORCE_ISO | RTC_CNTL_FORCE_PU); in rtc_sleep_init()
243 REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU); in rtc_sleep_init()
247 REG_CLR_BIT(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_FORCE); in rtc_sleep_init()
/hal_espressif-latest/components/hal/esp32h2/include/hal/
Dapm_ll.h107 REG_CLR_BIT(TEE_CLOCK_GATE_REG, TEE_CLK_EN); in apm_tee_ll_clk_gating_enable()
122 REG_CLR_BIT(HP_APM_REGION_FILTER_EN_REG, BIT(regn_num)); in apm_hp_ll_region_filter_enable()
137 REG_CLR_BIT(HP_APM_FUNC_CTRL_REG, BIT(hp_m_path)); in apm_hp_ll_m_filter_enable()
224 REG_CLR_BIT(HP_APM_INT_EN_REG, BIT(hp_m_path)); in apm_hp_ll_m_interrupt_enable()
238 REG_CLR_BIT(HP_APM_CLOCK_GATE_REG, HP_APM_CLK_EN); in apm_hp_ll_clk_gating_enable()
257 REG_CLR_BIT(PCR_RESET_EVENT_BYPASS_REG, PCR_RESET_EVENT_BYPASS_APM); in apm_hp_ll_reset_event_enable()
Decc_ll.h31 REG_CLR_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_PD); in ecc_ll_power_up()
32 REG_CLR_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_FORCE_PD); in ecc_ll_power_up()
37 REG_CLR_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_FORCE_PU); in ecc_ll_power_down()
105 REG_CLR_BIT(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH); in ecc_ll_set_curve()
117 REG_CLR_BIT(ECC_MULT_CONF_REG, ECC_MULT_MOD_BASE); in ecc_ll_set_mod_base()
Dregi2c_ctrl_ll.h25 REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); in regi2c_ctrl_ll_bbpll_calibration_start()
34 REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); in regi2c_ctrl_ll_bbpll_calibration_stop()
Dsar_ctrl_ll.h51 REG_CLR_BIT(PWDET_CONF_REG, PWDET_LL_SAR_POWER_FORCE_BIT); in sar_ctrl_ll_set_power_mode_from_pwdet()
57 REG_CLR_BIT(PWDET_CONF_REG, PWDET_LL_SAR_POWER_CNTL_BIT); in sar_ctrl_ll_set_power_mode_from_pwdet()
/hal_espressif-latest/components/hal/esp32c6/include/hal/
Dapm_ll.h107 REG_CLR_BIT(TEE_CLOCK_GATE_REG, TEE_CLK_EN); in apm_tee_ll_clk_gating_enable()
122 REG_CLR_BIT(HP_APM_REGION_FILTER_EN_REG, BIT(regn_num)); in apm_hp_ll_region_filter_enable()
137 REG_CLR_BIT(HP_APM_FUNC_CTRL_REG, BIT(hp_m_path)); in apm_hp_ll_m_filter_enable()
224 REG_CLR_BIT(HP_APM_INT_EN_REG, BIT(hp_m_path)); in apm_hp_ll_m_interrupt_enable()
238 REG_CLR_BIT(HP_APM_CLOCK_GATE_REG, HP_APM_CLK_EN); in apm_hp_ll_clk_gating_enable()
257 REG_CLR_BIT(PCR_RESET_EVENT_BYPASS_REG, PCR_RESET_EVENT_BYPASS_APM); in apm_hp_ll_reset_event_enable()
Decc_ll.h27 REG_CLR_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_PD); in ecc_ll_power_up()
28 REG_CLR_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_FORCE_PD); in ecc_ll_power_up()
33 REG_CLR_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_FORCE_PU); in ecc_ll_power_down()
77 REG_CLR_BIT(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH); in ecc_ll_set_curve()
Dregi2c_ctrl_ll.h23 REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); in regi2c_ctrl_ll_bbpll_calibration_start()
32 REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); in regi2c_ctrl_ll_bbpll_calibration_stop()
Dsar_ctrl_ll.h51 REG_CLR_BIT(PWDET_CONF_REG, PWDET_LL_SAR_POWER_FORCE_BIT); in sar_ctrl_ll_set_power_mode_from_pwdet()
57 REG_CLR_BIT(PWDET_CONF_REG, PWDET_LL_SAR_POWER_CNTL_BIT); in sar_ctrl_ll_set_power_mode_from_pwdet()
/hal_espressif-latest/components/esp_rom/patches/
Desp_rom_spiflash.c339 REG_CLR_BIT(SPI_USER_REG(0), SPI_USR_MOSI); in spi_cache_mode_switch()
345 REG_CLR_BIT(SPI_USER_REG(0), SPI_USR_MOSI); in spi_cache_mode_switch()
363 REG_CLR_BIT(SPI_USER_REG(0), SPI_USR_MOSI); in spi_cache_mode_switch()
365 REG_CLR_BIT(SPI_USER_REG(0), SPI_USR_DUMMY); in spi_cache_mode_switch()
443 REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY); in esp_rom_spiflash_erase_block()
463 REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY); in esp_rom_spiflash_erase_sector()
489 REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY); in esp_rom_spiflash_write()
560 REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_MOSI); in esp_rom_spiflash_read()
567 REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_MOSI); in esp_rom_spiflash_read()
571 REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY); in esp_rom_spiflash_read()
[all …]
/hal_espressif-latest/components/hal/esp32s3/include/hal/
Dregi2c_ctrl_ll.h56 REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); in regi2c_ctrl_ll_bbpll_calibration_start()
65 REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); in regi2c_ctrl_ll_bbpll_calibration_stop()
/hal_espressif-latest/components/hal/esp32c2/include/hal/
Dregi2c_ctrl_ll.h38 REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); in regi2c_ctrl_ll_bbpll_calibration_start()
47 REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); in regi2c_ctrl_ll_bbpll_calibration_stop()
Dsar_ctrl_ll.h66 REG_CLR_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_FORCE); in sar_ctrl_ll_set_power_mode_from_pwdet()
72 REG_CLR_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_CNTL); in sar_ctrl_ll_set_power_mode_from_pwdet()
/hal_espressif-latest/components/hal/esp32c3/include/hal/
Dsar_ctrl_ll.h67 REG_CLR_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_FORCE); in sar_ctrl_ll_set_power_mode_from_pwdet()
73 REG_CLR_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_CNTL); in sar_ctrl_ll_set_power_mode_from_pwdet()
/hal_espressif-latest/components/hal/esp32s2/include/hal/
Dsar_ctrl_ll.h70 REG_CLR_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_FORCE); in sar_ctrl_ll_set_power_mode_from_pwdet()
76 REG_CLR_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_CNTL); in sar_ctrl_ll_set_power_mode_from_pwdet()

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