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Searched refs:LP_SRAM_BASE (Results 1 – 10 of 10) sorted by relevance

/Zephyr-latest/soc/intel/intel_adsp/cavs/include/cavs25/
Dadsp_memory.h15 #define LP_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1))) macro
18 #define ROM_JUMP_ADDR (LP_SRAM_BASE + 0x10)
/Zephyr-latest/soc/intel/intel_adsp/ace/
Dmmu_ace30.c116 .start = (uint32_t)LP_SRAM_BASE,
117 .end = (uint32_t)(LP_SRAM_BASE + LP_SRAM_SIZE),
Dsram.c49 bbzero((void *)LP_SRAM_BASE, LP_SRAM_SIZE); in lp_sram_init()
Dpower.c264 UINT_TO_POINTER(LP_SRAM_BASE)), in pm_state_imr_restore()
322 memcpy(global_imr_ram_storage, (void *)LP_SRAM_BASE, LP_SRAM_SIZE); in pm_state_set()
Dace-link.ld149 org = LP_SRAM_BASE,
/Zephyr-latest/soc/intel/intel_adsp/ace/include/
Dadsp_memory.h21 #define LP_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1))) macro
24 #define ROM_JUMP_ADDR (LP_SRAM_BASE + 0x10)
/Zephyr-latest/tests/boards/intel_adsp/cache/src/
Dmain.c15 cached = (uint32_t *)LP_SRAM_BASE; in ZTEST()
/Zephyr-latest/soc/intel/intel_adsp/cavs/
Dsram.c142 bbzero((void *)LP_SRAM_BASE, LP_SRAM_SIZE); in lp_sram_init()
Dmultiprocessing.c67 (__sparse_force void __sparse_cache *)LP_SRAM_BASE); in soc_start_core()
/Zephyr-latest/soc/intel/intel_adsp/cavs/include/
Dxtensa-cavs-linker.ld134 org = LP_SRAM_BASE,