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Searched refs:GD32_RESET_SPI1 (Results 1 – 12 of 12) sorted by relevance

/Zephyr-latest/include/zephyr/dt-bindings/reset/
Dgd32f3x0.h45 #define GD32_RESET_SPI1 GD32_RESET_CONFIG(APB1RST, 14U) macro
Dgd32l23x.h49 #define GD32_RESET_SPI1 GD32_RESET_CONFIG(APB1RST, 14U) macro
Dgd32vf103.h50 #define GD32_RESET_SPI1 GD32_RESET_CONFIG(APB1RST, 14U) macro
Dgd32a50x.h49 #define GD32_RESET_SPI1 GD32_RESET_CONFIG(APB1RST, 14U) macro
Dgd32e10x.h57 #define GD32_RESET_SPI1 GD32_RESET_CONFIG(APB1RST, 14U) macro
Dgd32f403.h58 #define GD32_RESET_SPI1 GD32_RESET_CONFIG(APB1RST, 14U) macro
Dgd32e50x.h63 #define GD32_RESET_SPI1 GD32_RESET_CONFIG(APB1RST, 14U) macro
Dgd32f4xx.h73 #define GD32_RESET_SPI1 GD32_RESET_CONFIG(APB1RST, 14U) macro
/Zephyr-latest/dts/arm/gd/gd32a50x/
Dgd32a50x.dtsi153 resets = <&rctl GD32_RESET_SPI1>;
/Zephyr-latest/dts/riscv/gd/
Dgd32vf103.dtsi199 resets = <&rctl GD32_RESET_SPI1>;
/Zephyr-latest/dts/arm/gd/gd32f403/
Dgd32f403.dtsi134 resets = <&rctl GD32_RESET_SPI1>;
/Zephyr-latest/dts/arm/gd/gd32f4xx/
Dgd32f4xx.dtsi208 resets = <&rctl GD32_RESET_SPI1>;