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Searched refs:GD32_RESET_ADC0 (Results 1 – 10 of 10) sorted by relevance

/Zephyr-latest/include/zephyr/dt-bindings/reset/
Dgd32vf103.h35 #define GD32_RESET_ADC0 GD32_RESET_CONFIG(APB2RST, 9U) macro
Dgd32a50x.h61 #define GD32_RESET_ADC0 GD32_RESET_CONFIG(APB2RST, 9U) macro
Dgd32e10x.h36 #define GD32_RESET_ADC0 GD32_RESET_CONFIG(APB2RST, 9U) macro
Dgd32f403.h38 #define GD32_RESET_ADC0 GD32_RESET_CONFIG(APB2RST, 9U) macro
Dgd32e50x.h38 #define GD32_RESET_ADC0 GD32_RESET_CONFIG(APB2RST, 9U) macro
Dgd32f4xx.h95 #define GD32_RESET_ADC0 GD32_RESET_CONFIG(APB2RST, 8U) macro
/Zephyr-latest/dts/arm/gd/gd32a50x/
Dgd32a50x.dtsi164 resets = <&rctl GD32_RESET_ADC0>;
/Zephyr-latest/dts/riscv/gd/
Dgd32vf103.dtsi143 resets = <&rctl GD32_RESET_ADC0>;
/Zephyr-latest/dts/arm/gd/gd32f403/
Dgd32f403.dtsi156 resets = <&rctl GD32_RESET_ADC0>;
/Zephyr-latest/dts/arm/gd/gd32f4xx/
Dgd32f4xx.dtsi230 resets = <&rctl GD32_RESET_ADC0>;