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Searched refs:CK48M_SEL (Results 1 – 6 of 6) sorted by relevance

/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/
Df4_sdmmc48_pll.overlay10 /* clocks = <&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>;*/
11 clocks = <&rcc STM32_SRC_PLLI2S_Q CK48M_SEL(1)>;
/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dstm32f410_clock.h25 #define CK48M_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 27, DCKCFGR2_REG) macro
Dstm32f7_clock.h116 #define CK48M_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 27, DCKCFGR2_REG) macro
/Zephyr-latest/dts/arm/st/f4/
Dstm32f446.dtsi84 <&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>;
97 <&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>;
Dstm32f412.dtsi23 clocks = <&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>;
/Zephyr-latest/dts/arm/st/f7/
Dstm32f7.dtsi717 <&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>;
730 <&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>;
835 <&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>;