Home
last modified time | relevance | path

Searched refs:r0 (Results 1 – 25 of 80) sorted by relevance

1234

/Zephyr-latest/arch/arm/core/
Duserspace.S48 mov lr, r0
51 ldr r0, =_kernel
52 ldr r0, [r0, #_kernel_offset_to_current]
57 ldr r0, [r0, r1] /* priv stack ptr */
59 add r0, r0, r1
63 ldr r0, [r0, #_thread_offset_to_priv_stack_start] /* priv stack ptr */
65 add r0, r0, ip
67 ldr r0, [r0, #_thread_offset_to_priv_stack_start] /* priv stack ptr */
69 add r0, r0, ip
73 str r0, [ip, #_thread_offset_to_priv_stack_end] /* priv stack end */
[all …]
/Zephyr-latest/arch/arm/core/cortex_a_r/
Disr_wrapper.S53 push {r0}
57 mrs r0, spsr
58 and r0, #MODE_MASK
59 cmp r0, #MODE_USR
62 get_cpu r0
63 ldr r0, [r0, #___cpu_t_current_OFFSET]
67 str sp, [r0, #_thread_offset_to_sp_usr] /* sp_usr */
70 ldr sp, [r0, #_thread_offset_to_priv_stack_end] /* priv stack end */
74 pop {r0}
87 push {r0-r3, r12, lr}
[all …]
Dswap_helper.S48 push {r0, lr}
50 pop {r0, lr}
63 ldr r0, =_thread_offset_to_callee_saved
64 add r0, r2
68 stm r0, {r4-r11, sp}
72 ldrb r0, [r2, #_thread_offset_to_user_options]
73 tst r0, #K_FP_REGS /* arch_current_thread()->base.user_options & K_FP_REGS */
85 ldr r0, [r1, #___cpu_t_fp_ctx_OFFSET]
86 cmp r0, #0
89 vstmia r0!, {s0-s15}
[all …]
Dexc_exit.S34 push {r0-r1}
44 pop {r0-r1}
47 str r0, [sp, #8]
56 get_cpu r0
57 ldr r0, [r0, #___cpu_t_current_OFFSET]
59 ldr sp, [r0, #_thread_offset_to_sp_usr] /* sp_usr */
62 pop {r0-r1}
81 cmp r0, #0
145 ldr r0, [r3, #___cpu_t_nested_OFFSET]
146 cmp r0, #1
[all …]
Dexc.S53 stmfd sp, {r0-r3, r12, lr}^
60 mov r0, #FPEXC_EN
61 vmsr fpexc, r0
62 vmrs r0, fpscr
69 stm r2, {r0, r1}
75 mov r0, #0
76 str r0, [sp, #4]
77 str r0, [sp, #8]
85 mov r0, sp
88 mov r0, sp
[all …]
Dreset.S54 mrs r0, cpsr
55 and r0, r0, #MODE_MASK
56 cmp r0, #MODE_HYP
67 ldr r0, =HACTLR_INIT
68 mcr p15, 4, r0, c1, c0, 1
71 mrs r0, cpsr
72 bic r0, #MODE_MASK
73 orr r0, #MODE_SVC
74 msr spsr_cxsf, r0
76 ldr r0, =EL1_Reset_Handler
[all …]
Dcpu_idle.S27 push {r0, lr}
30 cmp r0, #0
48 pop {r0, lr}
55 push {r0, lr}
57 pop {r0, lr}
77 push {r0, lr}
79 pop {r0, lr}
94 cmp r0, #0
Dswitch.S49 ldrb r3, [r0, #_thread_offset_to_exception_depth]
63 ldr r3, [r0, #_thread_offset_to_tls]
73 add r2, r0, r2
78 push {r0, lr}
80 pop {r0, lr}
106 mrs r0, spsr
107 tst r0, #0x20
141 mov r0, sp
143 push {r0}
155 mov r0, sp
[all …]
/Zephyr-latest/arch/arc/core/
Dreset.S52 mov_s r0, 0
53 kflag r0
56 sflag r0
61 sr r0, [_ARC_V2_AUX_IRQ_ACT]
62 sr r0, [_ARC_V2_AUX_IRQ_CTRL]
64 sr r0, [_ARC_V2_AUX_IRQ_HINT]
69 MOVR r0, _VectorTable
71 sr r0, [_ARC_V2_IRQ_VECT_BASE_S]
73 SRR r0, [_ARC_V2_IRQ_VECT_BASE]
76 lr r0, [_ARC_V2_STATUS32]
[all …]
Duserspace.S66 pop_s r0
72 st.aw r0, [r5, -4]
107 push_s r0
118 mov_s r0, 0xaaaaaaaa
120 mov_s r0, 0x0
123 st.ab r0, [r4, 4]
136 _enable_stack_checking r0
144 lr r0, [_ARC_V2_STATUS32]
145 bset r0, r0, _ARC_V2_STATUS32_U_BIT
149 sr r0, [_ARC_V2_ERSTATUS]
[all …]
Disr_wrapper.S212 push r0
214 lr r0, [_ARC_V2_AUX_IRQ_ACT]
215 ffs r0, r0
216 cmp r0, 0
219 pop r0
222 lr r0, [_ARC_V2_STATUS32_P0]
223 st_s r0, [sp, ___isf_t_status32_OFFSET]
250 clri r0 /* do not interrupt exiting tickless idle operations */
260 seti r0
290 lr r0, [_ARC_V2_ICAUSE]
[all …]
Dfast_irq.S78 _check_and_inc_int_nest_counter r0, r1
81 mov_s r0, sp
125 push_s r0
142 _dec_int_nest_counter r0, r1
144 _check_nest_int_by_irq_act r0, r1
154 CMPR r0, 0
183 st r0, [r1, -4]
205 lr r0, [_ARC_V2_AUX_IRQ_ACT]
206 bbit0 r0, 31, _firq_from_kernel
208 lr r0, [_ARC_V2_STATUS32]
[all …]
Dfault_s.S41 lr r0,[_ARC_V2_ERSEC_STAT]
42 st_s r0, [sp, ___isf_t_sec_stat_OFFSET]
44 LRR r0, [_ARC_V2_ERET]
45 STR r0, sp, ___isf_t_pc_OFFSET
46 LRR r0, [_ARC_V2_ERSTATUS]
47 STR r0, sp, ___isf_t_status32_OFFSET
103 MOVR r0, sp
119 BREQR r0, 0, _exc_return_from_exc
126 MOVR r2, r0
169 mov_s r0, _ARC_V2_AUX_IRQ_ACT
[all …]
/Zephyr-latest/arch/arm/core/cortex_m/
Dreset.S73 movs.n r0, #0
75 strb r0, [r1]
80 movs.n r0, #0
81 msr CONTROL, r0
85 movs.n r0, #0
86 msr MSPLIM, r0
87 msr PSPLIM, r0
103 movs.n r0, #0
105 str r0, [r1]
108 ldr r0, =z_main_stack + CONFIG_MAIN_STACK_SIZE
[all …]
Dswap_helper.S59 push {r0, lr}
62 pop {r0, r1}
65 pop {r0, lr}
79 ldr r0, =_thread_offset_to_callee_saved
80 add r0, r2
87 stmea r0!, {r4-r7}
95 stmea r0!, {r3-r7}
97 stmia r0, {r4-r11, ip}
108 add r0, r2, #_thread_offset_to_preempt_float
109 vstmia r0, {s16-s31}
[all …]
/Zephyr-latest/arch/arc/core/secureshield/
Darc_secure.S81 lr r0, [_ARC_V2_STATUS32]
82 and r0, r0, 0x1e
83 asr r0, r0
84 or r0, r0, 0x30
91 btst r0, 4
93 mov r0, (CONFIG_NUM_IRQ_PRIO_LEVELS - 1)
97 cmp r0, r6
98 mov.hs r0, r6
100 and r0, r0, 0xf
101 brhs r0, ARC_N_IRQ_START_LEVEL, __seti_1
[all …]
/Zephyr-latest/soc/nxp/mcx/mcxw/
Dmcxw71_platform_init.S24 ldr r0, =0x14000000
27 cmp r0, r1
30 ldr r0, =0x14000000
37 stmia r0!, {r2 - r5}
38 cmp r0, r1
41 ldr r0, =0x30000000
44 stmia r0!, {r2 - r5}
45 cmp r0, r1
48 ldr r0, =0x3001a000
51 stmia r0!, {r2 - r5}
[all …]
/Zephyr-latest/soc/ti/lm3s6965/
Dreboot.S19 eors r0, r0
23 str r0, [r1, #0xd08] /* VTOR */
25 ldr r0, [r0, #4]
26 bx r0
32 ldr r0, =_SCS_ICSR_RETTOBASE
35 ands.w r0, r1
/Zephyr-latest/boards/nxp/mimxrt1062_fmurt6/
Dmimxrt1062_fmurt6-pinctrl.dtsi17 drive-strength = "r0-6";
26 drive-strength = "r0-6";
40 drive-strength = "r0-5";
48 drive-strength = "r0-5";
54 drive-strength = "r0-5";
66 drive-strength = "r0-6";
76 drive-strength = "r0-6";
86 drive-strength = "r0-6";
97 drive-strength = "r0-7";
107 drive-strength = "r0-7";
[all …]
/Zephyr-latest/boards/pjrc/teensy4/
Dteensy4-pinctrl.dtsi18 drive-strength = "r0-6";
31 drive-strength = "r0-5";
45 drive-strength = "r0-5";
58 drive-strength = "r0-6";
70 drive-strength = "r0-6";
82 drive-strength = "r0-6";
94 drive-strength = "r0-6";
107 drive-strength = "r0-6";
120 drive-strength = "r0-6";
135 drive-strength = "r0-6";
[all …]
/Zephyr-latest/boards/nxp/mimxrt1020_evk/
Dmimxrt1020_evk-pinctrl.dtsi17 drive-strength = "r0-6";
28 drive-strength = "r0-6";
40 drive-strength = "r0-5";
48 drive-strength = "r0-6";
58 drive-strength = "r0-5";
66 drive-strength = "r0-5";
74 drive-strength = "r0-5";
90 drive-strength = "r0-6";
101 drive-strength = "r0-6";
113 drive-strength = "r0-6";
[all …]
/Zephyr-latest/boards/nxp/mimxrt1024_evk/
Dmimxrt1024_evk-pinctrl.dtsi17 drive-strength = "r0-6";
27 drive-strength = "r0-6";
39 drive-strength = "r0-5";
47 drive-strength = "r0-6";
57 drive-strength = "r0-5";
65 drive-strength = "r0-5";
73 drive-strength = "r0-5";
89 drive-strength = "r0-6";
100 drive-strength = "r0-6";
112 drive-strength = "r0-6";
[all …]
/Zephyr-latest/boards/nxp/mimxrt1050_evk/
Dmimxrt1050_evk-pinctrl.dtsi18 drive-strength = "r0-6";
28 drive-strength = "r0-6";
47 drive-strength = "r0-6";
57 drive-strength = "r0-6";
70 drive-strength = "r0-5";
84 drive-strength = "r0-5";
96 drive-strength = "r0-6";
107 drive-strength = "r0-6";
117 drive-strength = "r0-6";
127 drive-strength = "r0-4";
[all …]
/Zephyr-latest/soc/nxp/lpc/lpc54xxx/gcc/
Dstartup_LPC54114_cm4.S50 ldr r0, [r6, #0]
51 ldr r1, [r0] /* r1 = CPU ID status */
63 ldr r0, [r6, #4]
64 ldr r3, [r0] /* r3 = SYSCON co-processor CPU control status */
78 ldr r0, [r6, #8]
79 ldr r2, [r0] /* r1 = SYSCON co-processor boot address */
84 ldr r0, [r6, #12]
85 ldr r1, [r0] /* r5 = SYSCON co-processor stack address */
/Zephyr-latest/boards/nxp/mimxrt1064_evk/
Dmimxrt1064_evk-pinctrl.dtsi18 drive-strength = "r0-6";
28 drive-strength = "r0-6";
47 drive-strength = "r0-6";
57 drive-strength = "r0-6";
70 drive-strength = "r0-5";
84 drive-strength = "r0-5";
96 drive-strength = "r0-6";
107 drive-strength = "r0-6";
117 drive-strength = "r0-6";
127 drive-strength = "r0-6";
[all …]

1234