1/*
2 * Copyright 2023 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/**
8 * @file
9 * @brief MCXW71 Platform-Specific Initialization
10 *
11 * MCXW71 SOC reset code that initializes RAM
12 * to prevent ECC causing faults, and calls SystemInit
13 */
14
15#include <zephyr/toolchain.h>
16#include <zephyr/linker/sections.h>
17
18_ASM_FILE_PROLOGUE
19
20GTEXT(soc_reset_hook)
21SECTION_SUBSEC_FUNC(TEXT,_reset_section,soc_reset_hook)
22
23.soc_reset_hook:
24    ldr r0, =0x14000000
25    ldr r1, =.ram_init_ctcm01
26    bics r1, #0x10000000
27    cmp r0, r1
28    bcc .ram_init_done
29.ram_init_ctcm01: /* Initialize ctcm01 */
30    ldr r0, =0x14000000
31    ldr r1, =0x14004000
32    ldr r2, =0
33    ldr r3, =0
34    ldr r4, =0
35    ldr r5, =0
36.loop01:
37    stmia r0!, {r2 - r5}
38    cmp r0, r1
39    bcc .loop01
40.ram_init_stcm012: /* Initialize stcm012 */
41    ldr r0, =0x30000000
42    ldr r1, =0x30010000
43.loop012:
44    stmia r0!, {r2 - r5}
45    cmp r0, r1
46    bcc .loop012
47.ram_init_stcm5:
48    ldr r0, =0x3001a000
49    ldr r1, =0x3001c000
50.loop5: /* Initialize stcm5 */
51    stmia r0!, {r2 - r5}
52    cmp r0, r1
53    bcc .loop5
54.ram_init_done:
55    b SystemInit
56