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Searched refs:sys_write32 (Results 26 – 50 of 191) sorted by relevance

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/Zephyr-latest/drivers/interrupt_controller/
Dintc_vim.c43 sys_write32(BIT(irq_bit_num), VIM_IRQSTS(irq_group_num)); in z_vim_irq_get_active()
54 sys_write32(0, VIM_IRQVEC); in z_vim_irq_eoi()
88 sys_write32(regval, VIM_INTTYPE(irq_group_num)); in z_vim_irq_priority_set()
103 sys_write32(BIT(irq_bit_num), VIM_INTR_EN_SET(irq_group_num)); in z_vim_irq_enable()
118 sys_write32(BIT(irq_bit_num), VIM_INTR_EN_CLR(irq_group_num)); in z_vim_irq_disable()
150 sys_write32(BIT(irq_bit_num), VIM_RAW(irq_group_num)); in z_vim_arm_enter_irq()
/Zephyr-latest/include/zephyr/arch/nios2/
Dasm_inline_gcc.h24 static ALWAYS_INLINE void sys_write32(uint32_t data, mm_reg_t addr) in sys_write32() function
36 sys_write32(data, addr); in sys_write8()
46 sys_write32(data, addr); in sys_write16()
/Zephyr-latest/soc/intel/intel_adsp/ace/
Dcomm_widget.h760 sys_write32(status, CW_BASE + USSTS); in cw_upstream_ready()
779 sys_write32(attr, CW_BASE + USATTR); in cw_upstream_set_attr()
789 sys_write32(address, CW_BASE + USLADDR); in cw_upstream_set_address16()
790 sys_write32(0, CW_BASE + USUADDR); in cw_upstream_set_address16()
800 sys_write32(data, CW_BASE + USDATA); in cw_upstream_set_data()
818 sys_write32(cmd, CW_BASE + USCMD); in cw_upstream_enable_sent_intr()
833 sys_write32(cmd, CW_BASE + USCMD); in cw_upstream_do_pw()
844 sys_write32(sts, CW_BASE + USSTS); in cw_upstream_clear_msgsent()
Dtimestamp.c53 sys_write32(tsctrl_temp, TSCTRL_ADDR); in intel_adsp_get_timestamp()
63 sys_write32(tsctrl_temp, TSCTRL_ADDR); in intel_adsp_get_timestamp()
69 sys_write32(tsctrl_temp, TSCTRL_ADDR); in intel_adsp_get_timestamp()
91 sys_write32(tsctrl_temp, TSCTRL_ADDR); in intel_adsp_get_timestamp()
/Zephyr-latest/drivers/serial/
Duart_xlnx_ps.c187 sys_write32(reg_val, reg_base + XUARTPS_CR_OFFSET); in xlnx_ps_disable_uart()
211 sys_write32(reg_val, reg_base + XUARTPS_CR_OFFSET); in xlnx_ps_enable_uart()
268 sys_write32(divisor, reg_base + XUARTPS_BAUDDIV_OFFSET); in set_baudrate()
269 sys_write32(generator, reg_base + XUARTPS_BAUDGEN_OFFSET); in set_baudrate()
309 sys_write32(reg_val, reg_base + XUARTPS_MR_OFFSET); in uart_xlnx_ps_init()
312 sys_write32(0x01U, reg_base + XUARTPS_RXWM_OFFSET); in uart_xlnx_ps_init()
315 sys_write32(XUARTPS_IXR_MASK, reg_base + XUARTPS_IDR_OFFSET); in uart_xlnx_ps_init()
323 sys_write32(XUARTPS_IXR_MASK, reg_base + XUARTPS_ISR_OFFSET); in uart_xlnx_ps_init()
380 sys_write32((uint32_t)(c & 0xFF), reg_base + XUARTPS_FIFO_OFFSET); in uart_xlnx_ps_poll_out()
634 sys_write32(mode_reg, reg_base + XUARTPS_MR_OFFSET); in uart_xlnx_ps_configure()
[all …]
Duart_intel_lw.c210 sys_write32(data->control_val, config->base in uart_intel_lw_poll_out()
213 sys_write32(c, config->base + INTEL_LW_UART_TXDATA_REG_OFFSET); in uart_intel_lw_poll_out()
223 sys_write32(data->control_val, config->base in uart_intel_lw_poll_out()
249 sys_write32(INTEL_LW_UART_CLEAR_STATUS_VAL, config->base in uart_intel_lw_init()
264 sys_write32(data->control_val, config->base + INTEL_LW_UART_CONTROL_REG_OFFSET); in uart_intel_lw_init()
315 sys_write32(INTEL_LW_UART_CLEAR_STATUS_VAL, config->base in uart_intel_lw_err_check()
380 sys_write32(divisor_val, config->base + INTEL_LW_UART_DIVISOR_REG_OFFSET); in uart_intel_lw_configure()
459 sys_write32(tx_data[ret_val++], config->base in uart_intel_lw_fifo_fill()
536 sys_write32(data->control_val, config->base + INTEL_LW_UART_CONTROL_REG_OFFSET); in uart_intel_lw_irq_tx_enable()
560 sys_write32(data->control_val, config->base + INTEL_LW_UART_CONTROL_REG_OFFSET); in uart_intel_lw_irq_tx_disable()
[all …]
Duart_bcm2711.c88 sys_write32(ch, base + BCM2711_MU_IO); in bcm2711_mu_lowlevel_putc()
102 sys_write32(0x0, base + BCM2711_MU_CNTL); in bcm2711_mu_lowlevel_init()
105 sys_write32(0x0, base + BCM2711_MU_IER); in bcm2711_mu_lowlevel_init()
108 sys_write32(BCM2711_MU_LCR_8BIT, base + BCM2711_MU_LCR); in bcm2711_mu_lowlevel_init()
111 sys_write32(divider - 1, base + BCM2711_MU_BAUD); in bcm2711_mu_lowlevel_init()
115 sys_write32(BCM2711_MU_CNTL_RX_ENABLE | BCM2711_MU_CNTL_TX_ENABLE, base + BCM2711_MU_CNTL); in bcm2711_mu_lowlevel_init()
195 sys_write32(BCM2711_MU_IER_TX_INTERRUPT, uart_data->uart_addr + BCM2711_MU_IER); in uart_bcm2711_irq_tx_enable()
202 sys_write32((uint32_t)(~BCM2711_MU_IER_TX_INTERRUPT), in uart_bcm2711_irq_tx_disable()
217 sys_write32(BCM2711_MU_IER_RX_INTERRUPT, uart_data->uart_addr + BCM2711_MU_IER); in uart_bcm2711_irq_rx_enable()
224 sys_write32((uint32_t)(~BCM2711_MU_IER_RX_INTERRUPT), in uart_bcm2711_irq_rx_disable()
Duart_altera.c194 sys_write32(c, config->base + ALTERA_AVALON_UART_TXDATA_REG_OFFSET); in uart_altera_poll_out()
214 sys_write32(ALTERA_AVALON_UART_CLEAR_STATUS_VAL, config->base in uart_altera_init()
229 sys_write32(data->control_val, config->base + ALTERA_AVALON_UART_CONTROL_REG_OFFSET); in uart_altera_init()
280 sys_write32(ALTERA_AVALON_UART_CLEAR_STATUS_VAL, config->base in uart_altera_err_check()
341 sys_write32(divisor_val, config->base + ALTERA_AVALON_UART_DIVISOR_REG_OFFSET); in uart_altera_configure()
415 sys_write32(*tx_data, config->base + ALTERA_AVALON_UART_TXDATA_REG_OFFSET); in uart_altera_fifo_fill()
480 sys_write32(data->control_val, config->base in uart_altera_fifo_read()
509 sys_write32(data->control_val, config->base + ALTERA_AVALON_UART_CONTROL_REG_OFFSET); in uart_altera_irq_tx_enable()
533 sys_write32(data->control_val, config->base + ALTERA_AVALON_UART_CONTROL_REG_OFFSET); in uart_altera_irq_tx_disable()
615 sys_write32(data->control_val, config->base + ALTERA_AVALON_UART_CONTROL_REG_OFFSET); in uart_altera_irq_rx_enable()
[all …]
/Zephyr-latest/drivers/misc/timeaware_gpio/
Dtimeaware_gpio_intel.c94 sys_write32(sys_read32(addr + CTL) & ~CTL_EN, addr + CTL); in tgpio_intel_pin_disable()
117 sys_write32(val, addr + PIV63_32); in tgpio_intel_periodic_output()
119 sys_write32(val, addr + PIV31_0); in tgpio_intel_periodic_output()
123 sys_write32(val, addr + COMPV63_32); in tgpio_intel_periodic_output()
125 sys_write32(val, addr + COMPV31_0); in tgpio_intel_periodic_output()
136 sys_write32(val, addr + CTL); in tgpio_intel_periodic_output()
166 sys_write32(val, addr + CTL); in tgpio_intel_config_external_timestamp()
169 sys_write32(sys_read32(addr + CTL) | CTL_EN, addr + CTL); in tgpio_intel_config_external_timestamp()
/Zephyr-latest/soc/brcm/bcmvk/viper/m7/
Dsoc.c24 sys_write32(data, LS_ICFG_PMON_LITE_CLK_CTRL); in soc_early_init_hook()
28 sys_write32(data, LS_ICFG_PMON_LITE_SW_RESETN); in soc_early_init_hook()
/Zephyr-latest/drivers/counter/
Dcounter_ace_v1x_art.c24 sys_write32(val, ACE_TSCTRL); in counter_ace_v1x_art_ionte_set()
34 sys_write32(val, ACE_TSCTRL); in counter_ace_v1x_art_cdmas_set()
44 sys_write32(val, ACE_TSCTRL); in counter_ace_v1x_art_ntk_set()
59 sys_write32(val, ACE_TSCTRL); in counter_ace_v1x_art_hhtse_set()
/Zephyr-latest/drivers/flash/
Dflash_cadence_nand_ll.c120 sys_write32(THREAD_VAL(thread), (base_address + CMD_STATUS_PTR_ADDR)); in cdns_nand_get_thrd_status()
167 sys_write32(SET_FEAT_ADDR(feat_addr), (base_address + CDNS_CMD_REG1)); in cdns_nand_pio_set_features()
168 sys_write32(feat_val, (base_address + CDNS_CMD_REG2)); in cdns_nand_pio_set_features()
173 sys_write32(status, (base_address + CDNS_CMD_REG0)); in cdns_nand_pio_set_features()
229 sys_write32(PHY_CTRL_REG_SDR, (base_address + PHY_CTRL_REG_OFFSET)); in cdns_nand_set_opr_mode()
230 sys_write32(PHY_TSEL_REG_SDR, (base_address + PHY_TSEL_REG_OFFSET)); in cdns_nand_set_opr_mode()
231 sys_write32(PHY_DQ_TIMING_REG_SDR, (base_address + PHY_DQ_TIMING_REG_OFFSET)); in cdns_nand_set_opr_mode()
232 sys_write32(PHY_DQS_TIMING_REG_SDR, (base_address + PHY_DQS_TIMING_REG_OFFSET)); in cdns_nand_set_opr_mode()
233 sys_write32(PHY_GATE_LPBK_CTRL_REG_SDR, (base_address + PHY_GATE_LPBK_OFFSET)); in cdns_nand_set_opr_mode()
234 sys_write32(PHY_DLL_MASTER_CTRL_REG_SDR, (base_address + PHY_DLL_MASTER_OFFSET)); in cdns_nand_set_opr_mode()
[all …]
Dflash_cadence_qspi_nor_ll.c52 sys_write32(CAD_QSPI_DEVSZ_ADDR_BYTES(addr_bytes) | in cad_qspi_configure_dev_size()
68 sys_write32(CAD_QSPI_DEV_OPCODE(opcode) | CAD_QSPI_DEV_INST_TYPE(instr_type) | in cad_qspi_set_read_config()
85 sys_write32(CAD_QSPI_DEV_OPCODE(opcode) | CAD_QSPI_DEV_ADDR_TYPE(addr_type) | in cad_qspi_set_write_config()
107 sys_write32(cfg, cad_params->reg_base + CAD_QSPI_CFG); in cad_qspi_timing_config()
109 sys_write32(CAD_QSPI_DELAY_CSSOT(cssot) | CAD_QSPI_DELAY_CSEOT(cseot) | in cad_qspi_timing_config()
126 sys_write32((sys_read32(cad_params->reg_base + CAD_QSPI_CFG) & CAD_QSPI_CFG_CS_MSK) | in cad_qspi_stig_cmd_helper()
130 sys_write32(cmd, cad_params->reg_base + CAD_QSPI_FLASHCMD); in cad_qspi_stig_cmd_helper()
131 sys_write32(cmd | CAD_QSPI_FLASHCMD_EXECUTE, cad_params->reg_base + CAD_QSPI_FLASHCMD); in cad_qspi_stig_cmd_helper()
229 sys_write32(input[0], cad_params->reg_base + CAD_QSPI_FLASHCMD_WRDATA0); in cad_qspi_stig_wr_cmd()
232 sys_write32(input[1], cad_params->reg_base + CAD_QSPI_FLASHCMD_WRDATA1); in cad_qspi_stig_wr_cmd()
[all …]
/Zephyr-latest/drivers/mm/
Dmm_drv_ti_rat.c53 sys_write32(0, RAT_CTRL(rat_base_addr, region_num)); in address_trans_set_region()
54 sys_write32(local_addr, RAT_BASE(rat_base_addr, region_num)); in address_trans_set_region()
55 sys_write32(system_addrL, RAT_TRANS_L(rat_base_addr, region_num)); in address_trans_set_region()
56 sys_write32(system_addrH, RAT_TRANS_H(rat_base_addr, region_num)); in address_trans_set_region()
57 sys_write32(RAT_CTRL_W(enable, size), RAT_CTRL(rat_base_addr, region_num)); in address_trans_set_region()
/Zephyr-latest/soc/brcm/bcmvk/viper/a72/
Dsoc.c28 sys_write32(data, LS_ICFG_PMON_LITE_CLK_CTRL); in soc_early_init_hook()
32 sys_write32(data, LS_ICFG_PMON_LITE_SW_RESETN); in soc_early_init_hook()
/Zephyr-latest/drivers/usb/udc/
Dudc_dwc2.c256 sys_write32(USB_DWC2_GRSTCTL_RXFFLSH, grstctl_reg); in dwc2_flush_rx_fifo()
269 sys_write32(grstctl, grstctl_reg); in dwc2_flush_tx_fifo()
306 sys_write32(dieptxf, (mem_addr_t)&base->dieptxf[f_idx]); in dwc2_set_txf()
462 sys_write32((is_periodic ? usb_dwc2_set_dieptsizn_mc(1 + addnl) : 0) | in dwc2_tx_fifo_write()
475 sys_write32((uint32_t)buf->data, in dwc2_tx_fifo_write()
504 sys_write32(diepctl, diepctl_reg); in dwc2_tx_fifo_write()
507 sys_write32(USB_DWC2_DIEPINT_INEPNAKEFF, diepint_reg); in dwc2_tx_fifo_write()
528 sys_write32(val, UDC_DWC2_EP_FIFO(base, ep_idx)); in dwc2_tx_fifo_write()
627 sys_write32(doeptsiz, doeptsiz_reg); in dwc2_prep_rx()
637 sys_write32((uint32_t)buf->data, in dwc2_prep_rx()
[all …]
/Zephyr-latest/drivers/dma/
Ddma_iproc_pax_v2.c292 sys_write32(val, RM_COMM_REG(pd, RM_COMM_CONTROL)); in rm_cfg_start()
303 sys_write32(val, RM_COMM_REG(pd, RM_COMM_CONTROL)); in rm_cfg_start()
304 sys_write32(RM_COMM_MSI_DISABLE_MASK, in rm_cfg_start()
312 sys_write32(val, RM_COMM_REG(pd, RM_COMM_AXI_READ_BURST_THRESHOLD)); in rm_cfg_start()
324 sys_write32(val, RM_COMM_REG(pd, RM_COMM_FIFO_FULL_THRESHOLD)); in rm_cfg_start()
329 sys_write32(val, RM_COMM_REG(pd, RM_COMM_CONTROL)); in rm_cfg_start()
332 sys_write32(RM_COMM_AE_TIMEOUT_VAL, in rm_cfg_start()
336 sys_write32(val, RM_COMM_REG(pd, RM_COMM_CONTROL)); in rm_cfg_start()
341 sys_write32(val, RM_COMM_REG(pd, RM_AE0_AE_CONTROL)); in rm_cfg_start()
343 sys_write32(val, RM_COMM_REG(pd, RM_AE0_AE_CONTROL)); in rm_cfg_start()
[all …]
Ddma_iproc_pax_v1.c271 sys_write32(val, RM_COMM_REG(pd, RM_COMM_CONTROL)); in rm_cfg_start()
275 sys_write32(val, RM_COMM_REG(pd, RM_COMM_CONTROL)); in rm_cfg_start()
278 sys_write32(RM_COMM_MSI_DISABLE_VAL, in rm_cfg_start()
283 sys_write32(val, RM_COMM_REG(pd, RM_COMM_CONTROL)); in rm_cfg_start()
286 sys_write32(RM_COMM_AE_TIMEOUT_VAL, RM_COMM_REG(pd, in rm_cfg_start()
290 sys_write32(val, RM_COMM_REG(pd, RM_COMM_CONTROL)); in rm_cfg_start()
295 sys_write32(val, RM_COMM_REG(pd, RM_AE0_AE_CONTROL)); in rm_cfg_start()
297 sys_write32(val, RM_COMM_REG(pd, RM_AE0_AE_CONTROL)); in rm_cfg_start()
302 sys_write32(val, RM_COMM_REG(pd, RM_COMM_AXI_CONTROL)); in rm_cfg_start()
305 sys_write32(RM_COMM_TIMER_CONTROL0_VAL, in rm_cfg_start()
[all …]
/Zephyr-latest/drivers/spi/
Dspi_sifive.c28 sys_write32(temp, addr); in sys_set_mask()
51 sys_write32((SF_SCKDIV_DIV_MASK & div), SPI_REG(dev, REG_SCKDIV)); in spi_config()
112 sys_write32((uint32_t) frame, SPI_REG(dev, REG_TXDATA)); in spi_sifive_send()
167 sys_write32(SF_CSMODE_OFF, SPI_REG(dev, REG_CSMODE)); in spi_sifive_xfer()
228 sys_write32(SF_CSMODE_OFF, SPI_REG(dev, REG_CSMODE)); in spi_sifive_transceive()
237 sys_write32(config->slave, SPI_REG(dev, REG_CSID)); in spi_sifive_transceive()
238 sys_write32(SF_CSMODE_OFF, SPI_REG(dev, REG_CSMODE)); in spi_sifive_transceive()
253 sys_write32(SF_CSMODE_HOLD, SPI_REG(dev, REG_CSMODE)); in spi_sifive_transceive()
/Zephyr-latest/drivers/dai/intel/dmic/
Ddmic.c124 sys_write32((sys_read32(dest) & (~mask)) | (val & mask), dest); in dai_dmic_update_bits()
130 sys_write32(val, dmic->reg_base + reg); in dai_dmic_write()
143 sys_write32(sys_read32(dmic->shim_base + DMICLCTL_OFFSET) | in dai_dmic_claim_ownership()
150 sys_write32(sys_read32(dmic->shim_base + DMICLCTL_OFFSET) & in dai_dmic_release_ownership()
177 sys_write32(sys_read32(base + DMICSYNC_OFFSET) | FIELD_PREP(DMICSYNC_SYNCPRD, val), in dai_dmic_set_sync_period()
179 sys_write32(sys_read32(base + DMICSYNC_OFFSET) | DMICSYNC_SYNCPU, in dai_dmic_set_sync_period()
187 sys_write32(sys_read32(base + DMICSYNC_OFFSET) | DMICSYNC_CMDSYNC, in dai_dmic_set_sync_period()
190 sys_write32(sys_read32(base + DMICSYNC_OFFSET) | FIELD_PREP(DMICSYNC_SYNCPRD, val), in dai_dmic_set_sync_period()
192 sys_write32(sys_read32(base + DMICSYNC_OFFSET) | DMICSYNC_CMDSYNC, in dai_dmic_set_sync_period()
201 sys_write32(sys_read32(base + DMICSYNC_OFFSET) & ~DMICSYNC_SYNCPRD, in dai_dmic_clear_sync_period()
[all …]
/Zephyr-latest/drivers/timer/
Dintel_adsp_timer.c66 sys_write32(sys_read32(DSPWCTCS_ADDR) & (~DSP_WCT_CS_TA(COMPARATOR_IDX)), in set_compare()
69 sys_write32((uint32_t)time, DSPWCT0C_LO_ADDR); in set_compare()
70 sys_write32((uint32_t)(time >> 32), DSPWCT0C_HI_ADDR); in set_compare()
73 sys_write32(sys_read32(DSPWCTCS_ADDR) | (DSP_WCT_CS_TA(COMPARATOR_IDX)), in set_compare()
115 sys_write32(sys_read32(DSPWCTCS_ADDR) | DSP_WCT_CS_TT(COMPARATOR_IDX), in compare_isr()
203 sys_write32(sys_read32(DSPWCTCS_ADDR) | ADSP_SHIM_DSPWCTCS_TTIE(COMPARATOR_IDX), in irq_init()
/Zephyr-latest/drivers/watchdog/
Dwdt_intel_adsp.h97 sys_write32(control, reg_addr); in intel_adsp_wdt_pause()
116 sys_write32(control, reg_addr); in intel_adsp_wdt_resume()
129 sys_write32(enable ? DSPCxWDTCS_STORE : 0, base + DSPCxWDTCS + DSPBRx_OFFSET(core)); in intel_adsp_wdt_reset_set()
Dwdt_xilinx_axi.c82 sys_write32(CSR0_EWDT1 | CSR0_WDS, config->base + REG_TWCSR0); in wdt_xilinx_axi_setup()
83 sys_write32(CSR1_EWDT2, config->base + REG_TWCSR1); in wdt_xilinx_axi_setup()
109 sys_write32(CSR0_WDS, config->base + REG_TWCSR0); in wdt_xilinx_axi_disable()
110 sys_write32(0, config->base + REG_TWCSR1); in wdt_xilinx_axi_disable()
165 sys_write32(timer_width, config->base + REG_MWR); in wdt_xilinx_axi_install_timeout()
192 sys_write32(twcsr0, config->base + REG_TWCSR0); in wdt_xilinx_axi_feed()
246 sys_write32(twcsr0, config->base + REG_TWCSR0); in z_impl_hwinfo_clear_reset_cause()
/Zephyr-latest/soc/microchip/mec/mec172x/
Ddevice_power.c53 sys_write32(pcr->CLK_REQ[i], vbm_addr); in soc_debug_sleep_clk_req()
57 sys_write32(pcr->SYS_SLP_CTRL, vbm_addr); in soc_debug_sleep_clk_req()
59 sys_write32(ecs->SLP_STS_MIRROR, vbm_addr); in soc_debug_sleep_clk_req()
198 sys_write32(ds_ctx.timers[i] | p->stop_mask, p->addr); in deep_sleep_save_timers()
200 sys_write32(0, p->addr); in deep_sleep_save_timers()
236 sys_write32(temp, p->addr); in deep_sleep_restore_timers()
238 sys_write32(ds_ctx.timers[i] & ~p->restore_mask, in deep_sleep_restore_timers()
273 sys_write32(regval & ~(MCHP_I2C_SMB_CFG_ENAB), addr); in deep_sleep_save_blocks()
329 sys_write32(ds_ctx.smb_info[n], addr); in deep_sleep_restore_blocks()
/Zephyr-latest/soc/intel/intel_adsp/common/
Dmem_window.c29 sys_write32(config->size | 0x7, DMWLO(config->base_addr)); in mem_win_init()
31 sys_write32((config->mem_base | ADSP_DMWBA_READONLY | ADSP_DMWBA_ENABLE), in mem_win_init()
34 sys_write32((config->mem_base | ADSP_DMWBA_ENABLE), DMWBA(config->base_addr)); in mem_win_init()

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