210 				sys_write32(data->control_val, config->base  in uart_intel_lw_poll_out()
213 				sys_write32(c, config->base + INTEL_LW_UART_TXDATA_REG_OFFSET);  in uart_intel_lw_poll_out()
223 				sys_write32(data->control_val, config->base  in uart_intel_lw_poll_out()
249 	sys_write32(INTEL_LW_UART_CLEAR_STATUS_VAL, config->base  in uart_intel_lw_init()
264 	sys_write32(data->control_val, config->base + INTEL_LW_UART_CONTROL_REG_OFFSET);  in uart_intel_lw_init()
315 	sys_write32(INTEL_LW_UART_CLEAR_STATUS_VAL, config->base  in uart_intel_lw_err_check()
380 			sys_write32(divisor_val, config->base + INTEL_LW_UART_DIVISOR_REG_OFFSET);  in uart_intel_lw_configure()
459 			sys_write32(tx_data[ret_val++], config->base  in uart_intel_lw_fifo_fill()
536 	sys_write32(data->control_val, config->base + INTEL_LW_UART_CONTROL_REG_OFFSET);  in uart_intel_lw_irq_tx_enable()
560 	sys_write32(data->control_val, config->base + INTEL_LW_UART_CONTROL_REG_OFFSET);  in uart_intel_lw_irq_tx_disable()
637 	sys_write32(data->control_val, config->base + INTEL_LW_UART_CONTROL_REG_OFFSET);  in uart_intel_lw_irq_rx_enable()
655 	sys_write32(data->control_val, config->base + INTEL_LW_UART_CONTROL_REG_OFFSET);  in uart_intel_lw_irq_rx_disable()
783 		sys_write32(data->control_val, config->base  in uart_intel_lw_dcts_isr()
790 			sys_write32(data->control_val, config->base  in uart_intel_lw_dcts_isr()
838 	sys_write32(INTEL_LW_UART_CLEAR_STATUS_VAL, config->base  in uart_intel_lw_isr()
866 		sys_write32(data->control_val, config->base  in uart_intel_lw_drv_cmd()
870 		sys_write32((uint8_t) p, config->base + INTEL_LW_UART_EOP_REG_OFFSET);  in uart_intel_lw_drv_cmd()
882 		sys_write32(data->control_val, config->base  in uart_intel_lw_drv_cmd()
895 		sys_write32(data->control_val, config->base  in uart_intel_lw_drv_cmd()
903 		sys_write32(data->control_val, config->base  in uart_intel_lw_drv_cmd()
911 		sys_write32(data->control_val, config->base  in uart_intel_lw_drv_cmd()
919 		sys_write32(data->control_val, config->base  in uart_intel_lw_drv_cmd()